Add that one IPR memory space address that we keep seeing

--HG--
extra : convert_revision : 81b365ac9ca8b33cae99107e5b1900f7c46f0866

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 0f9ad2cfc0bef76824c9c64b5290925e9ca503d9..00e97250f812069b923f55ace1e233b47ed2f83a 100644 (file)
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -90,8 +90,17 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
     if (req->paddr & PA_UNCACHED_BIT) {
         if (PA_IPR_SPACE(req->paddr)) {
             // IPR memory space not implemented
-            if (!req->xc->misspeculating())
-                panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+            if (!req->xc->misspeculating()) {
+                switch (req->paddr) {
+                  case 0xFFFFF00188:
+                    req->data = 0;
+                    break;
+
+                  default:
+                    panic("IPR memory space not implemented! PA=%x\n",
+                          req->paddr);
+                }
+            }
         } else {
             // mark request as uncacheable
             req->flags |= UNCACHEABLE;