*/
static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
{
+ const struct swizzle_data* sd;
unsigned int relevant;
int j;
if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
return 0;
- if (!lookup_native_swizzle(reg.Swizzle))
+ sd = lookup_native_swizzle(reg.Swizzle);
+ if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
return 0;
return 1;
{
const struct swizzle_data* sd = lookup_native_swizzle(swizzle);
- if (!sd) {
+ if (!sd || (src == RC_PAIR_PRESUB_SRC && sd->srcp_stride == 0)) {
fprintf(stderr, "Not a native swizzle: %08x\n", swizzle);
return 0;
}
inst_reader->U.I.SrcReg[src_index].Index = presub_opcode;
}
-static int is_presub_candidate(struct rc_instruction * inst)
+static int is_presub_candidate(
+ struct radeon_compiler * c,
+ struct rc_instruction * inst)
{
const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode);
unsigned int i;
return 0;
for(i = 0; i < info->NumSrcRegs; i++) {
- if (src_reads_dst_mask(inst->U.I.SrcReg[i], inst->U.I.DstReg))
+ struct rc_src_register src = inst->U.I.SrcReg[i];
+ if (src_reads_dst_mask(src, inst->U.I.DstReg))
+ return 0;
+
+ src.File = RC_FILE_PRESUB;
+ if (!c->SwizzleCaps->IsNative(inst->U.I.Opcode, src))
return 0;
}
return 1;
struct rc_src_register * src1 = NULL;
unsigned int i;
- if (!is_presub_candidate(inst_add))
+ if (!is_presub_candidate(c, inst_add))
return 0;
if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle)
{
unsigned int i, swz, mask;
- if (!is_presub_candidate(inst_add))
+ if (!is_presub_candidate(c, inst_add))
return 0;
mask = inst_add->U.I.DstReg.WriteMask;