add bold to exec summary, link to bigint analysis

diff --git a/openpower/pandoc_img.py b/openpower/pandoc_img.py
index 9eaf4056d000f24638a9a4b5ba567d5dc1f3bcc5..cdbce788a061edbc55cf1e929f2c0878262fd8bb 100755 (executable)
--- a/openpower/pandoc_img.py
+++ b/openpower/pandoc_img.py
@@ -87,6 +87,7 @@ def inlinenotes(k, v, f, meta):
                    'cr_int_predication' : 'CR Weird ops',
                    'sv/fclass' : 'FP Class ops',
                    'sv/biginteger' : 'Big Integer',
+                   'sv/biginteger/analysis' : 'Big Integer Analysis',
                    'isa/svfparith' : 'Floating Point pseudocode',
                    'isa/svfixedarith' : 'Fixed Point pseudocode',
                    'openpower/isa/branch' : 'Branch pseudocode',

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 3cd936c7df462acf4e1bbf2ef5bfc40e25a58519..00f78b6cda4beab44c3bccd34f0f3395aab5573b 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -14,7 +14,7 @@
 * (3): on specific operations.  See [[opcode_regs_deduped]] for full list
 * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries.
 * (5): SVP64 Vectorises Scalar instructions. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector operations.
-* (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger]]
+* (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger/analysis]]
 * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
 * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
 * (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index fa483e7dc8f507feab5818650a1d73b063b3186d..3a04d0bfd0d012c1c247dac2c02071eb8e7fc123 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -42,15 +42,15 @@ We invented Simple-V to be simple because we don't like complicated.
 
 Links to Simulator, installation scripts, and Unit tests:
 
-* Unit tests and simulator for Power ISA v3.0 and SVP64
+* **Unit tests and simulator for Power ISA v3.0 and SVP64**
   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD>
-* pypowersim tutorial <https://libre-soc.org/docs/pypowersim/>
-* several thousand more ISA unit tests
+* **pypowersim tutorial** <https://libre-soc.org/docs/pypowersim/>
+* **several thousand more ISA unit tests**
   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>
-* demo, showing 4.5x reduction in program size for MP3 decode, greatly
-  simplifies assembler development
+* **demo, showing 4.5x reduction in program size for MP3 decode, greatly
+  simplifies assembler development**
   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>
-* binutils support for SVP64 
+* **binutils support for SVP64**
   <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>
-* Documentation <https://libre-soc.org/docs>
-* Installation scripts <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD>
+* **Documentation** <https://libre-soc.org/docs>
+* **Installation scripts** <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD>