Add or-assignment operator

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index e6fa6361e076926d1d8a12bbf0e273fbd9860892..ea85bf52e123ebb18e2c00930a79468cffdf5639 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -526,6 +526,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 
 ".*" { return TOK_WILDCARD_CONNECT; }
 
+"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
+
 [-+]?[=*]> {
        if (!specify_mode) REJECT;
        yylval->string = new std::string(yytext);

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 15c231f3b98b1b02f4724b0b2df14ced514259a5..f7a73b00e0d06842fe844bb2972f79379bd98a97 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -259,7 +259,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
-%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
+%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
@@ -2334,6 +2334,14 @@ simple_behavioral_stmt:
                ast_stack.back()->children.push_back(node);
                SET_AST_NODE_LOC(node, @2, @5);
                append_attr(node, $1);
+       } |
+       attr lvalue TOK_OR_ASSIGN delay expr {
+               AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
+               SET_AST_NODE_LOC(or_node, @2, @5);
+               AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
+               SET_AST_NODE_LOC(node, @2, @5);
+               ast_stack.back()->children.push_back(node);
+               append_attr(node, $1);
        };
 
 // this production creates the obligatory if-else shift/reduce conflict