drop clock frequency for ulx3s to 25 mhz

diff --git a/Makefile b/Makefile
index 6ae68d4c423ab4bee5028548df19bf8a9e088154..672ca9fe14f8fe6cb7e0a50cd63f733d4a415754 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -161,10 +161,10 @@ FPGA_TARGET ?= ORANGE-CRAB
 ifeq ($(FPGA_TARGET), ULX3S)
 RESET_LOW=true
 CLK_INPUT=25000000
-CLK_FREQUENCY=40000000
+CLK_FREQUENCY=25000000
 LPF=constraints/orange-crab.lpf
 PACKAGE=CABGA381
-NEXTPNR_FLAGS=--um5g-85k --freq 40
+NEXTPNR_FLAGS=--um5g-85k --freq 25
 OPENOCD_JTAG_CONFIG=openocd/ulx3s.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
@@ -214,7 +214,7 @@ _fpga_files = fpga/soc_reset.vhdl \
        nonrandom.vhdl
 
 # use an alternative core (in verilog)
-EXTERNAL_CORE=true
+EXTERNAL_CORE=false
 ifeq ($(EXTERNAL_CORE),false)
     fpga_files = $(_fpga_files) $(_soc_files) $(core_files)
     synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)