radeonsi: move TCS_OUT_LAYOUT.PatchVerticesIn to lower bits

For a later patch.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 6f8fee6c28ecfc189fc2021d4789f489ce39716e..efdf80b961ec01c996ec724ce4b120235e505d37 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2014,7 +2014,7 @@ static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
 {
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        if (ctx->type == PIPE_SHADER_TESS_CTRL)
-               return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
+               return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
        else if (ctx->type == PIPE_SHADER_TESS_EVAL)
                return get_num_tcs_out_vertices(ctx);
        else

diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 42a1b9f107cccdbc6cbc088f345696b668db8f97..40947ffc0792bf0a83673d580d06eb2bf8db1a25 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -162,7 +162,7 @@ struct si_shader_context {
        /* Layout of TCS outputs / TES inputs:
         *   [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
         *            max = 32*32*4 + 32*4
-        *   [26:31] = gl_PatchVerticesIn, max = 32
+        *   [13:18] = gl_PatchVerticesIn, max = 32
         */
        int param_tcs_out_lds_layout;
        int param_tcs_offchip_addr_base64k;

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 06ef84d20da242fa870edef589e00faf689ee519..b245a383987048ced7a76b5c54e8d63e73e44648 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -233,7 +233,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 
        tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
                        S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
-       tcs_out_layout = output_patch_size / 4;
+       tcs_out_layout = (output_patch_size / 4) |
+                        (num_tcs_input_cp << 13);
        tcs_out_offsets = (output_patch0_offset / 16) |
                          ((perpatch_output_offset / 16) << 16);
        offchip_layout = *num_patches |
@@ -268,7 +269,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
                                      GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
                radeon_emit(cs, offchip_layout);
                radeon_emit(cs, tcs_out_offsets);
-               radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
+               radeon_emit(cs, tcs_out_layout);
        } else {
                unsigned ls_rsrc2 = ls_current->config.rsrc2;
 
@@ -288,7 +289,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
                        R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
                radeon_emit(cs, offchip_layout);
                radeon_emit(cs, tcs_out_offsets);
-               radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
+               radeon_emit(cs, tcs_out_layout);
                radeon_emit(cs, tcs_in_layout);
        }