Merge pull request #206 from Jbalkind/icachecleanup

Icache constants cleanup

diff --cc icache.vhdl
index 739e0478ae147174da24978201f479572fc60727,357f74da4cc2bfdbb10800ca93eb3b2b3354b7dd..dab2505cb37b9ece6a4a41c2a569cb4c9de30a23
--- 1/icache.vhdl
--- 2/icache.vhdl
+++ b/icache.vhdl
@@@ -115,10 -113,9 +116,10 @@@ architecture rtl of icache i
      subtype row_t is integer range 0 to BRAM_ROWS-1;
      subtype index_t is integer range 0 to NUM_LINES-1;
      subtype way_t is integer range 0 to NUM_WAYS-1;
 +    subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
  
      -- The cache data BRAM organized as described above for each way
-     subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
+     subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
  
      -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
      -- not handle a clean (commented) definition of the cache tags as a 3d