Revert "Fold loop"
authorEddie Hung <eddie@fpgeh.com>
Thu, 28 Nov 2019 05:55:56 +0000 (21:55 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 28 Nov 2019 05:55:56 +0000 (21:55 -0800)
This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.

backends/aiger/xaiger.cc

index a77949b4f32618151463ae6f7dbb48f9cb13dcad..627133314e47af23a7751ca7859dcf83d3cc6d33 100644 (file)
@@ -174,7 +174,6 @@ struct XAigerWriter
                                        if (bit != wirebit)
                                                alias_map[bit] = wirebit;
                                        input_bits.insert(wirebit);
-                                       undriven_bits.erase(bit);
                                }
 
                                if (wire->port_output || keep) {
@@ -182,8 +181,6 @@ struct XAigerWriter
                                                if (bit != wirebit)
                                                        alias_map[wirebit] = bit;
                                                output_bits.insert(wirebit);
-                                               if (!wire->port_input)
-                                                       unused_bits.erase(bit);
                                        }
                                        else
                                                log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@@ -191,6 +188,12 @@ struct XAigerWriter
                        }
                }
 
+               for (auto bit : input_bits)
+                       undriven_bits.erase(sigmap(bit));
+               for (auto bit : output_bits)
+                       if (!bit.wire->port_input)
+                               unused_bits.erase(bit);
+
                // TODO: Speed up toposort -- ultimately we care about
                //       box ordering, but not individual AIG cells
                dict<SigBit, pool<IdString>> bit_drivers, bit_users;