i965: Flip arguments to load_register_reg helpers.

load_register_imm and load_register_mem take the destination as the
first argument, so I'd like load_register_reg to do the same the sake
of consistency.  Otherwise, reading sequences of mixed LRI/LRM/LRR is
needlessly confusing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index e33e79fb6ce1f00d411f570d207426fcdf1100e6..5de6778430ca1029ecc69a5d52455a292417dcb4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -66,7 +66,7 @@ set_predicate_for_overflow_query(struct brw_context *brw,
    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
 
    hsw_overflow_result_to_gpr0(brw, query, count);
-   brw_load_register_reg64(brw, HSW_CS_GPR(0), MI_PREDICATE_SRC0);
+   brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0));
    brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index aedeeb55f6b9df8d332093fd419dd43072a15932..b278bdd477d2a007b10130867aa25cecd30a8d40 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1428,10 +1428,10 @@ void brw_load_register_imm32(struct brw_context *brw,
                              uint32_t reg, uint32_t imm);
 void brw_load_register_imm64(struct brw_context *brw,
                              uint32_t reg, uint64_t imm);
-void brw_load_register_reg(struct brw_context *brw, uint32_t src,
-                           uint32_t dest);
-void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
-                             uint32_t dest);
+void brw_load_register_reg(struct brw_context *brw, uint32_t dst,
+                           uint32_t src);
+void brw_load_register_reg64(struct brw_context *brw, uint32_t dst,
+                             uint32_t src);
 void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo,
                           uint32_t offset, uint32_t imm);
 void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo,

diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index 24f52a7d752ed37ac48f59c6d650c5b8e8f487c8..0f6c48379367005790557e8b584bcfb65924ced2 100644 (file)
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -154,7 +154,7 @@ static void
 shr_gpr0_by_2_bits(struct brw_context *brw)
 {
    shl_gpr0_by_30_bits(brw);
-   brw_load_register_reg(brw, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0));
+   brw_load_register_reg(brw, HSW_CS_GPR(0), HSW_CS_GPR(0) + 4);
    brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
 }
 

diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c
index f84063ded0478ae4530ce8f40f41f2e520018cc5..b7272db8b88c87d21148f19a4d9e4abc40b909c0 100644 (file)
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -98,7 +98,8 @@ tally_prims_written(struct brw_context *brw,
          brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
                                  START_OFFSET + i * sizeof(uint64_t));
          /* GPR2 = Ending Snapshot */
-         brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i), HSW_CS_GPR(2));
+         brw_load_register_reg64(brw, HSW_CS_GPR(2),
+                                 GEN7_SO_NUM_PRIMS_WRITTEN(i));
 
          BEGIN_BATCH(9);
          OUT_BATCH(HSW_MI_MATH | (9 - 2));

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 6bdd292d50edd381f5604b5bdd8dc9e81aef688b..7e3988c96b0a9a376ad32738a555e8fc52d48ec7 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -1218,7 +1218,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
  * Copies a 32-bit register.
  */
 void
-brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
+brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
 {
    assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);
 
@@ -1233,7 +1233,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
  * Copies a 64-bit register.
  */
 void
-brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
+brw_load_register_reg64(struct brw_context *brw, uint32_t dest, uint32_t src)
 {
    assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);