vexriscv_debug: use csr read()/write() accessors

CSR access widths can be different from register widths.  8-bit
registers are common.

The runtime-generated `read()` and `write()` functions handle this
mapping correctly.  When direct register accesses are handled, this
mapping is lost.

Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.

Signed-off-by: Sean Cross <sean@xobs.io>

diff --git a/litex/soc/tools/vexriscv_debug.py b/litex/soc/tools/vexriscv_debug.py
index cb5038330bdea07e3746bc3dd3bc64d36d8d431f..11276861e9e2012a8fe46d6290c0ee2a512c132c 100644 (file)
--- a/litex/soc/tools/vexriscv_debug.py
+++ b/litex/soc/tools/vexriscv_debug.py
@@ -35,9 +35,9 @@ class VexRiscvDebugBridge():
         if not hasattr(self, "rc"):\r
             self.rc = RemoteClient(csr_csv=self.args.csr)\r
             self.rc.open()\r
-            self.core_addr = self.rc.regs.cpu_or_bridge_debug_core.addr\r
-            self.data_addr = self.rc.regs.cpu_or_bridge_debug_data.addr\r
-            self.refresh_addr = self.rc.regs.cpu_or_bridge_debug_refresh.addr\r
+            self.core_reg = self.rc.regs.cpu_or_bridge_debug_core\r
+            self.data_reg = self.rc.regs.cpu_or_bridge_debug_data\r
+            self.refresh_reg = self.rc.regs.cpu_or_bridge_debug_refresh\r
 \r
     def _get_args(self):\r
         parser = argparse.ArgumentParser()\r
@@ -52,21 +52,21 @@ class VexRiscvDebugBridge():
         print("Accepted debugger connection from {}".format(address[0]))\r
 \r
     def _refresh_reg(self, reg):\r
-        self.rc.write(self.refresh_addr, reg)\r
+        self.refresh_reg.write(reg)\r
 \r
     def read_core(self):\r
         self._refresh_reg(0)\r
-        self.write_to_debugger(self.rc.read(self.core_addr))\r
+        self.write_to_debugger(self.core_reg.read())\r
 \r
     def read_data(self):\r
         self._refresh_reg(4)\r
-        self.write_to_debugger(self.rc.read(self.data_addr))\r
+        self.write_to_debugger(self.data_reg.read())\r
 \r
     def write_core(self, value):\r
-        self.rc.write(self.core_addr, value)\r
+        self.core_reg.write(value)\r
 \r
     def write_data(self, value):\r
-        self.rc.write(self.data_addr, value)\r
+        self.data_reg.write(value)\r
 \r
     def read_from_debugger(self):\r
         data = self.debugger.recv(10)\r