Fixed typo in port name

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 5a59a06b40c2f9b0f7a44612dbb92b837ad39799..b9cfbe66564bd065350f1640ff03b7941dbbfc08 100644 (file)
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
        
        reg[15:0] shreg = 0;
        
-       always @(posedge clk, negedge nRST) begin
+       always @(posedge CLK, negedge nRST) begin
                
                if(!nRST)
                        shreg = 0;