re PR target/57052 (missed optimization with rotate and mask)

	PR target/57052
	* config/rs6000/rs6000.md (rotlsi3_internal7): Rename to
	rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.
	(rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.
	Repeat for many other rotate/shift and mask patterns using subregs.
	Name lshiftrt insns.
	(ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition
	on WORDS_BIG_ENDIAN.

From-SVN: r198274

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fb7eb523624a0dee64b5d745de014ea7a03c63b9..05befdb223a8c154e132612b4934c496735c9d4f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2013-04-25  Alan Modra  <amodra@gmail.com>
+
+       PR target/57052
+       * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to
+       rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.
+       (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.
+       Repeat for many other rotate/shift and mask patterns using subregs.
+       Name lshiftrt insns.
+       (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition
+       on WORDS_BIG_ENDIAN.
+
 2013-04-25  Alan Modra  <amodra@gmail.com>
 
        * config.gcc: Support little-endian powerpc-linux targets.

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 14bd9bfb4325c5a28d990a41d8e6ad5ea61a0581..bae804a30da77e4b35d6d81163cdbe5ed5aaf6f2 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3798,20 +3798,33 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotlsi3_internal7"
+(define_insn "*rotlsi3_internal7le"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (zero_extend:SI
         (subreg:QI
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
-  ""
+  "!BYTES_BIG_ENDIAN"
+  "rlw%I2nm %0,%1,%h2,0xff"
+  [(set (attr "cell_micro")
+     (if_then_else (match_operand:SI 2 "const_int_operand" "")
+       (const_string "not")
+       (const_string "always")))])
+
+(define_insn "*rotlsi3_internal7be"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+       (zero_extend:SI
+        (subreg:QI
+         (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+                    (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
+  "BYTES_BIG_ENDIAN"
   "rlw%I2nm %0,%1,%h2,0xff"
   [(set (attr "cell_micro")
      (if_then_else (match_operand:SI 2 "const_int_operand" "")
        (const_string "not")
        (const_string "always")))])
 
-(define_insn "*rotlsi3_internal8"
+(define_insn "*rotlsi3_internal8le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:SI
                     (subreg:QI
@@ -3819,7 +3832,24 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  ""
+  "!BYTES_BIG_ENDIAN"
+  "@
+   rlwnm. %3,%1,%2,0xff
+   rlwinm. %3,%1,%h2,0xff
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotlsi3_internal8be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:SI
+                    (subreg:QI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
+                   (const_int 0)))
+   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
+  "BYTES_BIG_ENDIAN"
   "@
    rlwnm. %3,%1,%2,0xff
    rlwinm. %3,%1,%h2,0xff
@@ -3836,7 +3866,7 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
+  "!BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 3)
        (zero_extend:SI (subreg:QI
                      (rotate:SI (match_dup 1)
@@ -3846,7 +3876,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotlsi3_internal9"
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:SI
+                    (subreg:QI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                                (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
+                   (const_int 0)))
+   (clobber (match_scratch:SI 3 ""))]
+  "BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:SI (subreg:QI
+                     (rotate:SI (match_dup 1)
+                                (match_dup 2)) 3)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotlsi3_internal9le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:SI
                     (subreg:QI
@@ -3855,7 +3903,25 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  ""
+  "!BYTES_BIG_ENDIAN"
+  "@
+   rlwnm. %0,%1,%2,0xff
+   rlwinm. %0,%1,%h2,0xff
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotlsi3_internal9be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:SI
+                    (subreg:QI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
+                   (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+       (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
+  "BYTES_BIG_ENDIAN"
   "@
    rlwnm. %0,%1,%2,0xff
    rlwinm. %0,%1,%h2,0xff
@@ -3873,7 +3939,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  "reload_completed"
+  "!BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 0)
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -3881,20 +3947,48 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotlsi3_internal10"
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:SI
+                    (subreg:QI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                                (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
+                   (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+       (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
+  "BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotlsi3_internal10le"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:SI
         (subreg:HI
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
-  ""
+  "!BYTES_BIG_ENDIAN"
   "@
    rlwnm %0,%1,%2,0xffff
    rlwinm %0,%1,%h2,0xffff"
   [(set_attr "type" "var_shift_rotate,integer")])
 
+(define_insn "*rotlsi3_internal10be"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:SI
+        (subreg:HI
+         (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+                    (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
+  "BYTES_BIG_ENDIAN"
+  "@
+   rlwnm %0,%1,%2,0xffff
+   rlwinm %0,%1,%h2,0xffff"
+  [(set_attr "type" "var_shift_rotate,integer")])
 
-(define_insn "*rotlsi3_internal11"
+(define_insn "*rotlsi3_internal11le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:SI
                     (subreg:HI
@@ -3902,7 +3996,24 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  ""
+  "!BYTES_BIG_ENDIAN"
+  "@
+   rlwnm. %3,%1,%2,0xffff
+   rlwinm. %3,%1,%h2,0xffff
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotlsi3_internal11be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:SI
+                    (subreg:HI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
+                   (const_int 0)))
+   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
+  "BYTES_BIG_ENDIAN"
   "@
    rlwnm. %3,%1,%2,0xffff
    rlwinm. %3,%1,%h2,0xffff
@@ -3919,7 +4030,7 @@
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
+  "!BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 3)
        (zero_extend:SI (subreg:HI
                      (rotate:SI (match_dup 1)
@@ -3929,7 +4040,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotlsi3_internal12"
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:SI
+                    (subreg:HI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                                (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
+                   (const_int 0)))
+   (clobber (match_scratch:SI 3 ""))]
+  "BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:SI (subreg:HI
+                     (rotate:SI (match_dup 1)
+                                (match_dup 2)) 2)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotlsi3_internal12le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:SI
                     (subreg:HI
@@ -3938,7 +4067,25 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  ""
+  "!BYTES_BIG_ENDIAN"
+  "@
+   rlwnm. %0,%1,%2,0xffff
+   rlwinm. %0,%1,%h2,0xffff
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotlsi3_internal12be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:SI
+                    (subreg:HI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
+                   (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+       (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
+  "BYTES_BIG_ENDIAN"
   "@
    rlwnm. %0,%1,%2,0xffff
    rlwinm. %0,%1,%h2,0xffff
@@ -3956,7 +4103,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  "reload_completed"
+  "!BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 0)
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -3964,6 +4111,23 @@
                    (const_int 0)))]
   "")
 
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:SI
+                    (subreg:HI
+                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                                (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
+                   (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+       (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
+  "BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
 (define_insn "ashlsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -4277,16 +4441,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*lshiftrt_internal1le"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (zero_extend:SI
         (subreg:QI
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
   "rlwinm %0,%1,%s2,0xff")
 
-(define_insn ""
+(define_insn "*lshiftrt_internal1be"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+       (zero_extend:SI
+        (subreg:QI
+         (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+                      (match_operand:SI 2 "const_int_operand" "i")) 3)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
+  "rlwinm %0,%1,%s2,0xff")
+
+(define_insn "*lshiftrt_internal2le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
        (compare:CC
         (zero_extend:SI
@@ -4295,7 +4468,23 @@
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
         (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
+  "@
+   rlwinm. %3,%1,%s2,0xff
+   #"
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "4,8")])
+
+(define_insn "*lshiftrt_internal2be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:QI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+                       (match_operand:SI 2 "const_int_operand" "i,i")) 3))
+        (const_int 0)))
+   (clobber (match_scratch:SI 3 "=r,r"))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
   "@
    rlwinm. %3,%1,%s2,0xff
    #"
@@ -4311,7 +4500,7 @@
                        (match_operand:SI 2 "const_int_operand" "")) 0))
         (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
   [(set (match_dup 3)
        (zero_extend:SI (subreg:QI
           (lshiftrt:SI (match_dup 1)
@@ -4321,7 +4510,26 @@
                    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:QI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                       (match_operand:SI 2 "const_int_operand" "")) 3))
+        (const_int 0)))
+   (clobber (match_scratch:SI 3 ""))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:SI (subreg:QI
+          (lshiftrt:SI (match_dup 1)
+                       (match_dup 2)) 3)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*lshiftrt_internal3le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
        (compare:CC
         (zero_extend:SI
@@ -4331,7 +4539,24 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
+  "@
+   rlwinm. %0,%1,%s2,0xff
+   #"
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "4,8")])
+
+(define_insn "*lshiftrt_internal3be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:QI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+                       (match_operand:SI 2 "const_int_operand" "i,i")) 3))
+        (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
   "@
    rlwinm. %0,%1,%s2,0xff
    #"
@@ -4348,7 +4573,7 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
   [(set (match_dup 0)
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -4356,16 +4581,43 @@
                    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:QI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                       (match_operand:SI 2 "const_int_operand" "")) 3))
+        (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+       (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*lshiftrt_internal4le"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (zero_extend:SI
         (subreg:HI
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
   "rlwinm %0,%1,%s2,0xffff")
 
-(define_insn ""
+(define_insn "*lshiftrt_internal4be"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+       (zero_extend:SI
+        (subreg:HI
+         (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+                      (match_operand:SI 2 "const_int_operand" "i")) 2)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
+  "rlwinm %0,%1,%s2,0xffff")
+
+(define_insn "*lshiftrt_internal5le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
        (compare:CC
         (zero_extend:SI
@@ -4374,7 +4626,23 @@
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
         (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
+  "@
+   rlwinm. %3,%1,%s2,0xffff
+   #"
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "4,8")])
+
+(define_insn "*lshiftrt_internal5be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:HI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+                       (match_operand:SI 2 "const_int_operand" "i,i")) 2))
+        (const_int 0)))
+   (clobber (match_scratch:SI 3 "=r,r"))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
   "@
    rlwinm. %3,%1,%s2,0xffff
    #"
@@ -4390,7 +4658,7 @@
                        (match_operand:SI 2 "const_int_operand" "")) 0))
         (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
   [(set (match_dup 3)
        (zero_extend:SI (subreg:HI
           (lshiftrt:SI (match_dup 1)
@@ -4400,7 +4668,26 @@
                    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:HI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                       (match_operand:SI 2 "const_int_operand" "")) 2))
+        (const_int 0)))
+   (clobber (match_scratch:SI 3 ""))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:SI (subreg:HI
+          (lshiftrt:SI (match_dup 1)
+                       (match_dup 2)) 2)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*lshiftrt_internal5le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
        (compare:CC
         (zero_extend:SI
@@ -4410,7 +4697,24 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
+  "@
+   rlwinm. %0,%1,%s2,0xffff
+   #"
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "4,8")])
+
+(define_insn "*lshiftrt_internal5be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:HI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+                       (match_operand:SI 2 "const_int_operand" "i,i")) 2))
+        (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
   "@
    rlwinm. %0,%1,%s2,0xffff
    #"
@@ -4427,7 +4731,7 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
+  "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
   [(set (match_dup 0)
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -4435,6 +4739,24 @@
                    (const_int 0)))]
   "")
 
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC
+        (zero_extend:SI
+         (subreg:HI
+          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                       (match_operand:SI 2 "const_int_operand" "")) 2))
+        (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+       (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
+  "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -6319,11 +6641,11 @@
   [(set_attr "type" "two,three")
    (set_attr "length" "8,12")])
 
-(define_insn "*ashrdisi3_noppc64"
+(define_insn "*ashrdisi3_noppc64be"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
                                 (const_int 32)) 4))]
-  "TARGET_32BIT && !TARGET_POWERPC64"
+  "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
   "*
 {
   if (REGNO (operands[0]) == REGNO (operands[1]))
@@ -6610,19 +6932,31 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal7"
+(define_insn "*rotldi3_internal7le"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:DI
         (subreg:QI
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
   "@
    rldcl %0,%1,%2,56
    rldicl %0,%1,%H2,56"
   [(set_attr "type" "var_shift_rotate,integer")])
 
-(define_insn "*rotldi3_internal8"
+(define_insn "*rotldi3_internal7be"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:DI
+        (subreg:QI
+         (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+                    (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
+  "@
+   rldcl %0,%1,%2,56
+   rldicl %0,%1,%H2,56"
+  [(set_attr "type" "var_shift_rotate,integer")])
+
+(define_insn "*rotldi3_internal8le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:QI
@@ -6630,7 +6964,24 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %3,%1,%2,56
+   rldicl. %3,%1,%H2,56
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal8be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:QI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %3,%1,%2,56
    rldicl. %3,%1,%H2,56
@@ -6647,7 +6998,7 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 3)
        (zero_extend:DI (subreg:QI
                      (rotate:DI (match_dup 1)
@@ -6657,7 +7008,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal9"
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:QI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 ""))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:DI (subreg:QI
+                     (rotate:DI (match_dup 1)
+                                (match_dup 2)) 7)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotldi3_internal9le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:QI
@@ -6666,7 +7035,25 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %0,%1,%2,56
+   rldicl. %0,%1,%H2,56
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal9be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:QI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
+       (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %0,%1,%2,56
    rldicl. %0,%1,%H2,56
@@ -6684,7 +7071,7 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 0)
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -6692,19 +7079,48 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal10"
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:QI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "")
+       (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotldi3_internal10le"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:DI
         (subreg:HI
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl %0,%1,%2,48
+   rldicl %0,%1,%H2,48"
+  [(set_attr "type" "var_shift_rotate,integer")])
+
+(define_insn "*rotldi3_internal10be"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:DI
+        (subreg:HI
+         (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+                    (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
   "@
    rldcl %0,%1,%2,48
    rldicl %0,%1,%H2,48"
   [(set_attr "type" "var_shift_rotate,integer")])
 
-(define_insn "*rotldi3_internal11"
+(define_insn "*rotldi3_internal11le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:HI
@@ -6712,7 +7128,24 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %3,%1,%2,48
+   rldicl. %3,%1,%H2,48
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal11be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:HI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %3,%1,%2,48
    rldicl. %3,%1,%H2,48
@@ -6729,7 +7162,7 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 3)
        (zero_extend:DI (subreg:HI
                      (rotate:DI (match_dup 1)
@@ -6739,7 +7172,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal12"
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:HI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 ""))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:DI (subreg:HI
+                     (rotate:DI (match_dup 1)
+                                (match_dup 2)) 6)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotldi3_internal12le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:HI
@@ -6748,7 +7199,25 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %0,%1,%2,48
+   rldicl. %0,%1,%H2,48
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal12be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:HI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
+       (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %0,%1,%2,48
    rldicl. %0,%1,%H2,48
@@ -6766,7 +7235,7 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 0)
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -6774,19 +7243,48 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal13"
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:HI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "")
+       (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotldi3_internal13le"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (zero_extend:DI
         (subreg:SI
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl %0,%1,%2,32
+   rldicl %0,%1,%H2,32"
+  [(set_attr "type" "var_shift_rotate,integer")])
+
+(define_insn "*rotldi3_internal13be"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+       (zero_extend:DI
+        (subreg:SI
+         (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+                    (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
   "@
    rldcl %0,%1,%2,32
    rldicl %0,%1,%H2,32"
   [(set_attr "type" "var_shift_rotate,integer")])
 
-(define_insn "*rotldi3_internal14"
+(define_insn "*rotldi3_internal14le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:SI
@@ -6794,7 +7292,24 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %3,%1,%2,32
+   rldicl. %3,%1,%H2,32
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal14be"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:SI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %3,%1,%2,32
    rldicl. %3,%1,%H2,32
@@ -6811,7 +7326,7 @@
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 3)
        (zero_extend:DI (subreg:SI
                      (rotate:DI (match_dup 1)
@@ -6821,7 +7336,25 @@
                    (const_int 0)))]
   "")
 
-(define_insn "*rotldi3_internal15"
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:SI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 ""))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 3)
+       (zero_extend:DI (subreg:SI
+                     (rotate:DI (match_dup 1)
+                                (match_dup 2)) 4)))
+   (set (match_dup 0)
+       (compare:CC (match_dup 3)
+                   (const_int 0)))]
+  "")
+
+(define_insn "*rotldi3_internal15le"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
        (compare:CC (zero_extend:DI
                     (subreg:SI
@@ -6830,7 +7363,25 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+  "@
+   rldcl. %0,%1,%2,32
+   rldicl. %0,%1,%H2,32
+   #
+   #"
+  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+   (set_attr "length" "4,4,8,8")])
+
+(define_insn "*rotldi3_internal15be"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+       (compare:CC (zero_extend:DI
+                    (subreg:SI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
+                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
+       (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+  "TARGET_64BIT && BYTES_BIG_ENDIAN"
   "@
    rldcl. %0,%1,%2,32
    rldicl. %0,%1,%H2,32
@@ -6848,7 +7399,7 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
   [(set (match_dup 0)
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
    (set (match_dup 3)
@@ -6856,6 +7407,23 @@
                    (const_int 0)))]
   "")
 
+(define_split
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+       (compare:CC (zero_extend:DI
+                    (subreg:SI
+                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                                (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "")
+       (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+  "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+  [(set (match_dup 0)
+       (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
+   (set (match_dup 3)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  "")
+
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")