Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
+ (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
+ (mips_after_parse_args): Translate EVA to EVA_R6.
+ * testsuite/gas/mips/ase-errors-1.s: Add new instructions.
+ * testsuite/gas/mips/eva.s: Likewise.
+ * testsuite/gas/mips/ase-errors-1.l: Check errors for
+ new instructions.
+ * testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
+
2019-05-06 Alan Modra <amodra@gmail.com>
* symbols.c (symbol_relc_make_sym): Do not access sym->sy_value
/* Clear combination ASE flags, which need to be recalculated based on
updated regular ASE settings. */
- opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
+ opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6);
if (enabled_p)
opts->ase |= ase->flags;
mask |= ASE_MIPS16E2_MT;
}
+ /* The EVA Extension has instructions which are only valid when the R6 ISA
+ is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
+ present. */
+ if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa))
+ {
+ opts->ase |= ASE_EVA_R6;
+ mask |= ASE_EVA_R6;
+ }
+
return mask;
}
goto ld;
case M_LLDP_AB:
case M_LLWP_AB:
+ case M_LLWPE_AB:
s = ip->insn_mo->name;
fmt = "t,d,s";
ll_sc_paired = 1;
goto ld_st;
case M_SCDP_AB:
case M_SCWP_AB:
+ case M_SCWPE_AB:
s = ip->insn_mo->name;
fmt = "t,d,s";
ll_sc_paired = 1;
file_mips_opts.isa = arch_info->isa;
file_mips_opts.init_ase = arch_info->ase;
+ /* The EVA Extension has instructions which are only valid when the R6 ISA
+ is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
+ present. */
+ if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa))
+ file_mips_opts.ase |= ASE_EVA_R6;
+
/* Set up initial mips_opts state. */
mips_opts = file_mips_opts;
.*:117: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
.*:120: Error: opcode not supported.* `ginvi \$a0'
# ----------------------------------------------------------------------------
+.*:127: Error: opcode not supported .* `llwpe \$2,\$3,\$4'
+.*:128: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
+.*:131: Error: opcode not supported .* `llwpe \$2,\$3,\$4'
+.*:132: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
.set noginv
ginvi $a0 # ERROR: ginv not enabled
+ .set mips32r6
+ .set eva
+ llwpe $2, $3, $4 # OK
+ scwpe $2, $3, $4 # OK
+ .set noeva
+ llwpe $2, $3, $4 # ERROR: eva not enabled
+ scwpe $2, $3, $4 # ERROR: eva not enabled
+ .set mips32r5
+ .set eva
+ llwpe $2, $3, $4 # ERROR: only avaialable on R6
+ scwpe $2, $3, $4 # ERROR: only avaialable on R6
+
# There should be no errors after this.
.set fp=32
.set mips1
prefe 11,($12)
prefe 13,MYDATA
prefe 5,%lo(foo)($6)
+
+ .ifdef r6
+ llwpe $2, $3, 0x1234
+ llwpe $2, $0, 0xabcd($0)
+ llwpe $0, $3, %lo(sync_mem)
+ llwpe $2, $2, 0xffffffff01234567($0)
+ llwpe $0, $0, sync_mem
+ scwpe $2, $3, 0x1234
+ scwpe $2, $0, 0xabcd($0)
+ scwpe $0, $3, %lo(sync_mem)
+ scwpe $2, $2, 0xffffffff01234567($0)
+ scwpe $0, $0, sync_mem
+ .endif
[ 0-9a-f]+: 24c10000 addiu \$1,\$6,0
[ 0-9a-f]+: R_MIPS_LO16 foo
[ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\)
+[ 0-9a-f]+: 24021234 li \$2,4660
+[ 0-9a-f]+: 7c42186e llwpe \$2,\$3,\$2
+[ 0-9a-f]+: 3c020001 lui \$2,0x1
+[ 0-9a-f]+: 2442abcd addiu \$2,\$2,-21555
+[ 0-9a-f]+: 7c42006e llwpe \$2,\$0,\$2
+[ 0-9a-f]+: 24030000 li \$3,0
+ [0-9a-f]+: R_MIPS_LO16 sync_mem
+[ 0-9a-f]+: 7c60186e llwpe \$0,\$3,\$3
+[ 0-9a-f]+: 3c020123 lui \$2,0x123
+[ 0-9a-f]+: 24424567 addiu \$2,\$2,17767
+[ 0-9a-f]+: 7c42106e llwpe \$2,\$2,\$2
+[ 0-9a-f]+: 3c010000 lui \$1,0x0
+ [0-9a-f]+: R_MIPS_HI16 sync_mem
+[ 0-9a-f]+: 24210000 addiu \$1,\$1,0
+ [0-9a-f]+: R_MIPS_LO16 sync_mem
+[ 0-9a-f]+: 7c20006e llwpe \$0,\$0,\$1
+[ 0-9a-f]+: 24011234 li \$1,4660
+[ 0-9a-f]+: 7c22185e scwpe \$2,\$3,\$1
+[ 0-9a-f]+: 3c010001 lui \$1,0x1
+[ 0-9a-f]+: 2421abcd addiu \$1,\$1,-21555
+[ 0-9a-f]+: 7c22005e scwpe \$2,\$0,\$1
+[ 0-9a-f]+: 24010000 li \$1,0
+ [0-9a-f]+: R_MIPS_LO16 sync_mem
+[ 0-9a-f]+: 7c20185e scwpe \$0,\$3,\$1
+[ 0-9a-f]+: 3c010123 lui \$1,0x123
+[ 0-9a-f]+: 24214567 addiu \$1,\$1,17767
+[ 0-9a-f]+: 7c22105e scwpe \$2,\$2,\$1
+[ 0-9a-f]+: 3c010000 lui \$1,0x0
+ [0-9a-f]+: R_MIPS_HI16 sync_mem
+[ 0-9a-f]+: 24210000 addiu \$1,\$1,0
+ [0-9a-f]+: R_MIPS_LO16 sync_mem
+[ 0-9a-f]+: 7c20005e scwpe \$0,\$0,\$1
#pass
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * opcode/mips.h (ASE_EVA_R6): New macro.
+ (M_LLWPE_AB, M_SCWPE_AB): New enum values.
+
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
#define ASE_LOONGSON_EXT 0x00800000
/* Loongson EXTensions R2 (EXT2) instructions. */
#define ASE_LOONGSON_EXT2 0x01000000
+/* The Enhanced VA Scheme (EVA) extension has instructions which are
+ only valid for the R6 ISA. */
+#define ASE_EVA_R6 0x02000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
M_LLDP_AB,
M_LLE_AB,
M_LLWP_AB,
+ M_LLWPE_AB,
M_LQ_AB,
M_LW_AB,
M_LWE_AB,
M_SCDP_AB,
M_SCE_AB,
M_SCWP_AB,
+ M_SCWPE_AB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): Add ISA
+ argument and set ASE_EVA_R6 appropriately.
+ (set_default_mips_dis_options): Pass ISA to above.
+ (parse_mips_dis_option): Likewise.
+ * mips-opc.c (EVAR6): New macro.
+ (mips_builtin_opcodes): Add llwpe, scwpe.
+
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
/* Calculate combination ASE flags from regular ASE flags. */
static unsigned long
-mips_calculate_combination_ases (unsigned long opcode_ases)
+mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases)
{
unsigned long combination_ases = 0;
combination_ases |= ASE_XPA_VIRT;
if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
combination_ases |= ASE_MIPS16E2_MT;
+ if ((opcode_ases & ASE_EVA)
+ && ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6
+ || (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6))
+ combination_ases |= ASE_EVA_R6;
return combination_ases;
}
mips_ase |= ASE_MDMX;
}
#endif
- mips_ase |= mips_calculate_combination_ases (mips_ase);
+ mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
}
/* Parse an ASE disassembler option and set the corresponding global
if (parse_mips_ase_option (option))
{
- mips_ase |= mips_calculate_combination_ases (mips_ase);
+ mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
return;
}
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
+#define EVAR6 ASE_EVA_R6
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"llwpe", "t,d,s", 0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 },
+{"llwpe", "t,d,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"scwpe", "t,d,s", 0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 },
+{"scwpe", "t,d,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },
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