reword

diff --git a/updates/003_2018dec04_microarchitecture.mdwn b/updates/003_2018dec04_microarchitecture.mdwn
index 2d6af927aa01f81540e8f0cba6ec55cc4a5b39df..55bae1d960970140e1b486fb7559891a3bc357bf 100644 (file)
--- a/updates/003_2018dec04_microarchitecture.mdwn
+++ b/updates/003_2018dec04_microarchitecture.mdwn
@@ -29,11 +29,12 @@ another uses register 10, *both* of them could actually be "redirected"
 to use register 112, for example.  One of those could even be changed
 to 32-bit operations whilst the other is set to 16-bit element widths.
 
-Our initial thoughts were to try a standard simple in-order SIMD architecture,
+Our initial thoughts advocated a standard simple in-order SIMD architecture,
 with predication bits passed down into the SIMD ALUs.  If a bit is "off",
 that "lane" within the ALU does not calculate a result, saving power.
-However, a pre-analysis engine is required that re-orders the registers,
-packs lanes of data together so that it fits into one SIMD ALU, and, on
+However, in SV, when the element width is set to 32, 16 or 8-bit, a
+pre-issue engine is required that re-orders *parts* of the registers,
+packing lanes of data together so that it fits into one SIMD ALU, and, on
 exit from the ALU, it may be necessary to split and "redirect" parts of the
 data to *multiple* actual 64-bit registers.  In other words, bit-level
 (or byte-level) manipulation is required, both pre- and post- ALU.
@@ -48,7 +49,9 @@ different paradigm from standard vector processors, where a loop allocates
 elements to "lanes", and if a predication bit is not set, the lane
 runs "empty".  By contrast, with the multi-issue execution model, an
 operation that is predicated out means that the element-based instruction
-does not even make it into the instruction queue.  Thus, unlike in a
+does not even make it into the instruction queue, leaving it free for
+use by following instructions, even in the same cycle, and even if the
+operation is totally different.  Thus, unlike in a
 traditional vectore architecture, ALUs may be occupied by elements from 
 other "Lanes", because of the pre-existing decoupling between the multi-issue
 instruction queue and the ALUs.