lib.fifo: fix simulation read/write methods to take only one cycle.

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index d52c144a307cd4323e6f16a2030cb956936afd4b..9bf927f23f0eca42042c8854c1363d3bbf118ceb 100644 (file)
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -63,11 +63,10 @@ class FIFOInterface:
     def read(self):
         """Read method for simulation."""
         assert (yield self.readable)
-        value = (yield self.dout)
         yield self.re.eq(1)
         yield
+        value = (yield self.dout)
         yield self.re.eq(0)
-        yield
         return value
 
     def write(self, data):
@@ -77,7 +76,6 @@ class FIFOInterface:
         yield self.we.eq(1)
         yield
         yield self.we.eq(0)
-        yield
 
 
 def _incr(signal, modulo):