grr, save/restore in verilator, use class member os.read/write

not daft "<<" or ">>" operator-overload

diff --git a/Makefile b/Makefile
index 387ce0099f034cc91d36720444662b293da1d581..e4a46eac8bfd613c81c7bbe16a2aa72dd7fef9af 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,7 @@
 GHDL ?= ghdl
 GHDLFLAGS=--std=08 -frelaxed
 CFLAGS=-O3 -Wall
+CXXFLAGS=-g -g
 
 GHDLSYNTH ?= ghdl.so
 YOSYS     ?= yosys
@@ -226,7 +227,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 # --top-module toplevel
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-       verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" \
+       verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
     --assert \
     --cc microwatt.v \
     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \

diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index 5c91f92d949249e15d8718845fdf02ad37ca8c2f..8f30f0fe18f412837c53e88264cef5c953c8147a 100644 (file)
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -8,7 +8,7 @@
 #include "Vmicrowatt.h"
 #include "verilated.h"
 #include "verilated_vcd_c.h"
-#include "uart-verilated.h"
+#include "uart-verilator.h"
 
 /*
  * Current simulation time
@@ -72,7 +72,7 @@ void save_model(vluint64_t time, Vmicrowatt* topp)
 
     os.open(fname);
     os << main_time;  // user code must save the timestamp, etc
-    os << *uart;
+    os.write(uart, sizeof(*uart));
     os << *topp;
 }
 
@@ -84,7 +84,7 @@ void restore_model(vluint64_t time, Vmicrowatt* topp)
     struct uart_tx_state uart;
     os.open(fname);
     os >> main_time;
-    os >> uart;
+    os.read(&uart, sizeof(uart));
     os >> *topp;
     uart_restore(&uart);
 }