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update image size
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 27 Apr 2020 10:37:35 +0000 (11:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 27 Apr 2020 10:37:35 +0000 (11:37 +0100)
3d_gpu/architecture/memory_and_cache.mdwn patch | blob | history

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index 271ab68d952739de2ab363706ab8d7e24bb4320f..d3f5dd51f164b59d910a00967e9986109eb07ab8 100644 (file)
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -8,7 +8,7 @@ roadmap ASIC.
 
 Basic diagram:
 
-[[!img 180nm_single_core_testasic_memlayout.jpg size="500x"]]
+[[!img 180nm_single_core_testasic_memlayout.jpg size="600x"]]
 
 * Eight LD/ST Function Units with 2 ports each (one for aligned,
   one for misaligned), each connecting to one of a pair of L0
http://libre-riscv.org ikiwiki