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CSKY: Add CPU CK803r3.
authorCooper Qu <cooper.qu@linux.alibaba.com>
Wed, 2 Sep 2020 06:06:03 +0000 (14:06 +0800)
committerLifang Xia <lifang_xia@c-sky.com>
Wed, 2 Sep 2020 06:21:31 +0000 (14:21 +0800)
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.

gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.

include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.

opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.

gas/ChangeLog patch | blob | history
gas/config/tc-csky.c patch | blob | history
include/ChangeLog patch | blob | history
include/opcode/csky.h patch | blob | history
opcodes/ChangeLog patch | blob | history
opcodes/csky-opc.h patch | blob | history

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 303a332a0a4576b7846e41191d665c7982105d42..167f357febb4dbd61598d785ba3b6b23fe736b9e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * config/tc-csky.c (csky_cpus): Add ck803r3.
+       (CSKY_ISA_803R3): Define.
+       (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
+
 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
        * testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index f85c44ddb051c239c0be81e275e05a3c806795a9..0ed39e46e73c2b0452ab5ff4d60456c0f6c12323 100644 (file)
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -620,8 +620,8 @@ const struct csky_cpu_info csky_cpus[] =
   /* CK803 series.  */
 #define CSKY_ISA_803    (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP)
 #define CSKY_ISA_803R1  (CSKY_ISA_803 | CSKYV2_ISA_3E3R1)
-#define CSKY_ISA_803R2  (CSKY_ISA_803 | CSKYV2_ISA_3E3R1 | CSKYV2_ISA_3E3R2)
 #define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3)
+#define CSKY_ISA_EDSP   (CSKYV2_ISA_3E3R3 | CSKY_ISA_DSP_ENHANCE)
   {"ck803", CSKY_ARCH_803, CSKY_ISA_803 },
   {"ck803h", CSKY_ARCH_803, CSKY_ISA_803 },
   {"ck803t", CSKY_ARCH_803, CSKY_ISA_803 | CSKY_ISA_TRUST},
@@ -643,31 +643,35 @@ const struct csky_cpu_info csky_cpus[] =
   {"ck803htr1", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST},
   {"ck803fr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
   {"ck803fhr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
-  {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
-  {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
-  {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
-  {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
-  {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
-  {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
+  {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
+  {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
+  {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+  {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+  {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
+  {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
   {"ck803ftr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
-  {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
-  {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+  {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+  {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
 
+#define CSKY_ISA_803R2  (CSKY_ISA_803R1 | CSKYV2_ISA_3E3R2)
   {"ck803r2", CSKY_ARCH_803, CSKY_ISA_803R2},
   {"ck803hr2", CSKY_ARCH_803, CSKY_ISA_803R2},
   {"ck803tr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
   {"ck803htr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
   {"ck803fr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
   {"ck803fhr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
-  {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
-  {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
-  {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
-  {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
-  {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
-  {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
+  {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
+  {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
+  {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+  {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+  {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
+  {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
   {"ck803ftr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
-  {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
-  {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+  {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+  {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+
+#define CSKY_ISA_803R3  (CSKY_ISA_803R2 | CSKYV2_ISA_3E3R3)
+  {"ck803r3", CSKY_ARCH_803, CSKY_ISA_803R3},
 
   {"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 },
   {"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP},
diff --git a/include/ChangeLog b/include/ChangeLog
index 9daa866d72522c5e11cae1db409112fda17aee81..c6f00b35d6920b0d375991952c4a3f8e59ce0dff 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
+
 2020-08-31  Alan Modra  <amodra@gmail.com>
 
        PR 26493
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index 493e822a5a30cae26cd8f6ec49b67990b38cfe6b..ab2b21092710d7683c58bc00db98dd82e7fb4250 100644 (file)
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -31,6 +31,7 @@
 #define CSKYV2_ISA_3E3R1    (1L << 6)
 #define CSKYV2_ISA_3E3R2    (1L << 7)
 #define CSKYV2_ISA_10E60    (1L << 8)
+#define CSKYV2_ISA_3E3R3    (1L << 9)
 
 #define CSKY_ISA_TRUST      (1L << 11)
 #define CSKY_ISA_CACHE      (1L << 12)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a4e95aea5e41c24a3f34e59ffcc7060a70bfa681..8481a13e08bd65dbb0bebe4826ef45bb9f504ca2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * csky-opc.h (csky_v2_opcodes): Move divul and divsl
+       to CSKYV2_ISA_3E3R3 instruction set.
+
 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
        * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 54203aaab7eb2457a28475548f30dd3f5f260e8b..5e2f1a58695b8473056ddbdbd6a3172f38775c4d 100644 (file)
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -5321,13 +5321,13 @@ const struct csky_opcode csky_v2_opcodes[] =
                        (0_4, AREG, OPRND_SHIFT_0_BIT),
                        (16_20, AREG, OPRND_SHIFT_0_BIT),
                        (21_25, AREG, OPRND_SHIFT_0_BIT)),
-         CSKY_ISA_DSP_ENHANCE),
+         CSKYV2_ISA_3E3R3),
     OP32 ("divsl",
          OPCODE_INFO3 (0xf800e2e0,
                        (0_4, AREG, OPRND_SHIFT_0_BIT),
                        (16_20, AREG, OPRND_SHIFT_0_BIT),
                        (21_25, AREG, OPRND_SHIFT_0_BIT)),
-         CSKY_ISA_DSP_ENHANCE),
+         CSKYV2_ISA_3E3R3),
     OP32 ("mulaca.s8",
          OPCODE_INFO3 (0xf800e4c0,
                        (0_4, AREG, OPRND_SHIFT_0_BIT),