update Vexriscv

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5..3b5b0e7c13ae2b7874fac40cbb3c4dc75deb1e1d 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5
+Subproject commit 3b5b0e7c13ae2b7874fac40cbb3c4dc75deb1e1d