void
TimingSimpleCPU::resume()
{
+ DPRINTF(SimpleCPU, "Resume\n");
if (_status != SwitchedOut && _status != Idle) {
assert(system->getMemoryMode() == Enums::timing);
void
TimingSimpleCPU::activateContext(int thread_num, int delay)
{
+ DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
+
assert(thread_num == 0);
assert(thread);
void
TimingSimpleCPU::suspendContext(int thread_num)
{
+ DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
+
assert(thread_num == 0);
assert(thread);
void
TimingSimpleCPU::fetch()
{
+ DPRINTF(SimpleCPU, "Fetch\n");
+
if (!curStaticInst || !curStaticInst->isDelayedCommit())
checkForInterrupts();
void
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
+ DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
+
// received a response from the icache: execute the received
// instruction
assert(!pkt->isError());