lasmi: reduce latencies by 1 cycle

diff --git a/milkymist/dfii/__init__.py b/milkymist/dfii/__init__.py
index c6fc834e943d4220756b702564b562a64cdb556a..22a5bcd5e905bcc8d9280d54df84796941e94610 100644 (file)
--- a/milkymist/dfii/__init__.py
+++ b/milkymist/dfii/__init__.py
@@ -13,7 +13,6 @@ class PhaseInjector(Module, AutoCSR):
        
                ###
 
-               wrdata_en_adv = Signal()
                self.comb += [
                        If(self._command_issue.re,
                                phase.cs_n.eq(~self._command.storage[0]),
@@ -28,15 +27,12 @@ class PhaseInjector(Module, AutoCSR):
                        ),
                        phase.address.eq(self._address.storage),
                        phase.bank.eq(self._baddress.storage),
-                       wrdata_en_adv.eq(self._command_issue.re & self._command.storage[4]),
+                       phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
                        phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
                        phase.wrdata.eq(self._wrdata.storage),
                        phase.wrdata_mask.eq(0)
                ]
-               self.sync += [
-                       phase.wrdata_en.eq(wrdata_en_adv),
-                       If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
-               ]
+               self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
 
 class DFIInjector(Module, AutoCSR):
        def __init__(self, a, ba, d, nphases=1):

diff --git a/milkymist/lasmicon/multiplexer.py b/milkymist/lasmicon/multiplexer.py
index d1260b4081230350926b8bd840f5f79074f36f1f..13911dcfeb08ec71313cc883b528146c948fe01d 100644 (file)
--- a/milkymist/lasmicon/multiplexer.py
+++ b/milkymist/lasmicon/multiplexer.py
@@ -65,7 +65,6 @@ class _Steerer(Module):
                        else:
                                return cmd.stb & getattr(cmd, attr)
                for phase, sel in zip(dfi.phases, self.sel):
-                       wrdata_en_adv = Signal()
                        self.comb += [
                                phase.cke.eq(1),
                                phase.cs_n.eq(0)
@@ -77,8 +76,7 @@ class _Steerer(Module):
                                phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]),
                                phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]),
                                phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]),
-                               wrdata_en_adv.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel]),
-                               phase.wrdata_en.eq(wrdata_en_adv)
+                               phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
                        ]
 
 class Multiplexer(Module):

diff --git a/top.py b/top.py
index 77a4ce9b50dac7971b120d5d91136a5527abce8c..910b90ed24d40d361a567d442820d653606bea2b 100644 (file)
--- a/top.py
+++ b/top.py
@@ -44,8 +44,8 @@ sdram_timing = lasmicon.TimingSettings(
        tRFC=ns(70),
        
        CL=3,
-       read_latency=5,
-       write_latency=1,
+       read_latency=4,
+       write_latency=0,
 
        read_time=32,
        write_time=16

diff --git a/verilog/s6ddrphy/s6ddrphy.v b/verilog/s6ddrphy/s6ddrphy.v
index 86001f14f68f4603546d0856536e75b0b3b835b2..dc4a49b6ee3e9d0316ddd45cf5a14553f675dfa9 100644 (file)
--- a/verilog/s6ddrphy/s6ddrphy.v
+++ b/verilog/s6ddrphy/s6ddrphy.v
@@ -2,12 +2,12 @@
  * 1:2 frequency-ratio DDR PHY for Spartan-6
  *
  * Assert dfi_wrdata_en and present the data 
- * on dfi_wrdata_mask/dfi_wrdata in the cycle
- * immediately following the write command.
+ * on dfi_wrdata_mask/dfi_wrdata in the same
+ * cycle as the write command.
  *
  * Assert dfi_rddata_en in the same cycle as the read
  * command. The data will come back on dfi_rddata
- * 5 cycles later, along with the assertion of
+ * 4 cycles later, along with the assertion of
  * dfi_rddata_valid.
  *
  * This PHY only supports CAS Latency 3.
@@ -75,39 +75,6 @@ module s6ddrphy #(
  * Command/address
  */
 
-reg [NUM_AD-1:0] r0_dfi_address_p0;
-reg [NUM_BA-1:0] r0_dfi_bank_p0;
-reg r0_dfi_cs_n_p0;
-reg r0_dfi_cke_p0;
-reg r0_dfi_ras_n_p0;
-reg r0_dfi_cas_n_p0;
-reg r0_dfi_we_n_p0;
-reg [NUM_AD-1:0] r0_dfi_address_p1;
-reg [NUM_BA-1:0] r0_dfi_bank_p1;
-reg r0_dfi_cs_n_p1;
-reg r0_dfi_cke_p1;
-reg r0_dfi_ras_n_p1;
-reg r0_dfi_cas_n_p1;
-reg r0_dfi_we_n_p1;
-       
-always @(posedge sys_clk) begin
-       r0_dfi_address_p0 <= dfi_address_p0;
-       r0_dfi_bank_p0 <= dfi_bank_p0;
-       r0_dfi_cs_n_p0 <= dfi_cs_n_p0;
-       r0_dfi_cke_p0 <= dfi_cke_p0;
-       r0_dfi_ras_n_p0 <= dfi_ras_n_p0;
-       r0_dfi_cas_n_p0 <= dfi_cas_n_p0;
-       r0_dfi_we_n_p0 <= dfi_we_n_p0;
-       
-       r0_dfi_address_p1 <= dfi_address_p1;
-       r0_dfi_bank_p1 <= dfi_bank_p1;
-       r0_dfi_cs_n_p1 <= dfi_cs_n_p1;
-       r0_dfi_cke_p1 <= dfi_cke_p1;
-       r0_dfi_ras_n_p1 <= dfi_ras_n_p1;
-       r0_dfi_cas_n_p1 <= dfi_cas_n_p1;
-       r0_dfi_we_n_p1 <= dfi_we_n_p1;
-end
-
 reg phase_sel;
 always @(posedge clk2x_270)
        phase_sel <= sys_clk;
@@ -128,21 +95,21 @@ reg r_dfi_cas_n_p1;
 reg r_dfi_we_n_p1;
        
 always @(posedge clk2x_270) begin
-       r_dfi_address_p0 <= r0_dfi_address_p0;
-       r_dfi_bank_p0 <= r0_dfi_bank_p0;
-       r_dfi_cs_n_p0 <= r0_dfi_cs_n_p0;
-       r_dfi_cke_p0 <= r0_dfi_cke_p0;
-       r_dfi_ras_n_p0 <= r0_dfi_ras_n_p0;
-       r_dfi_cas_n_p0 <= r0_dfi_cas_n_p0;
-       r_dfi_we_n_p0 <= r0_dfi_we_n_p0;
+       r_dfi_address_p0 <= dfi_address_p0;
+       r_dfi_bank_p0 <= dfi_bank_p0;
+       r_dfi_cs_n_p0 <= dfi_cs_n_p0;
+       r_dfi_cke_p0 <= dfi_cke_p0;
+       r_dfi_ras_n_p0 <= dfi_ras_n_p0;
+       r_dfi_cas_n_p0 <= dfi_cas_n_p0;
+       r_dfi_we_n_p0 <= dfi_we_n_p0;
        
-       r_dfi_address_p1 <= r0_dfi_address_p1;
-       r_dfi_bank_p1 <= r0_dfi_bank_p1;
-       r_dfi_cs_n_p1 <= r0_dfi_cs_n_p1;
-       r_dfi_cke_p1 <= r0_dfi_cke_p1;
-       r_dfi_ras_n_p1 <= r0_dfi_ras_n_p1;
-       r_dfi_cas_n_p1 <= r0_dfi_cas_n_p1;
-       r_dfi_we_n_p1 <= r0_dfi_we_n_p1;
+       r_dfi_address_p1 <= dfi_address_p1;
+       r_dfi_bank_p1 <= dfi_bank_p1;
+       r_dfi_cs_n_p1 <= dfi_cs_n_p1;
+       r_dfi_cke_p1 <= dfi_cke_p1;
+       r_dfi_ras_n_p1 <= dfi_ras_n_p1;
+       r_dfi_cas_n_p1 <= dfi_cas_n_p1;
+       r_dfi_we_n_p1 <= dfi_we_n_p1;
 end
 
 always @(posedge clk2x_270) begin
@@ -367,10 +334,10 @@ end
 assign drive_dqs = r2_dfi_wrdata_en;
 
 wire rddata_valid;
-reg [5:0] rddata_sr;
+reg [4:0] rddata_sr;
 assign dfi_rddata_valid_w0 = rddata_sr[0];
 assign dfi_rddata_valid_w1 = rddata_sr[0];
 always @(posedge sys_clk)
-       rddata_sr <= {dfi_rddata_en_p0, rddata_sr[5:1]};
+       rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
 
 endmodule