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Ignore merging past ffs that we are not properly merging
author
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 29 Apr 2022 12:35:02 +0000
(14:35 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 29 Apr 2022 12:35:02 +0000
(14:35 +0200)
frontends/verific/verific.cc
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diff --git
a/frontends/verific/verific.cc
b/frontends/verific/verific.cc
index 284d5db31f6374648426acb6a44e61e672881873..d19d837ffcca33316b8271ffb1d664c32ad06f36 100644
(file)
--- a/
frontends/verific/verific.cc
+++ b/
frontends/verific/verific.cc
@@
-987,6
+987,7
@@
void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
for (auto cell : candidates)
{
+ if (cell->type != ID($dff)) continue;
SigBit clock = cell->getPort(ID::CLK);
bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
database[make_pair(clock, int(clock_pol))].insert(cell);