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Put sysclk2x back under system reset control
authorRaptor Engineering Development Team <support@raptorengineering.com>
Sun, 10 Apr 2022 02:31:27 +0000 (21:31 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Sun, 10 Apr 2022 02:31:27 +0000 (21:31 -0500)
examples/ecp5_crg.py patch | blob | history

diff --git a/examples/ecp5_crg.py b/examples/ecp5_crg.py
index 82ff66d193c924209440e82bc27e291b2667285a..cda8a9932b34a75ed9426a1b0a24e1023a80aed1 100644 (file)
--- a/examples/ecp5_crg.py
+++ b/examples/ecp5_crg.py
@@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
-        cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True)
+        cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)