(no commit message)

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index e65cefce17635ee67fd511ed8b54c3062fc5f82f..15d7d11d64d52344a35a11693a9960dfa5410c89 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -7,11 +7,11 @@ Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode:
 
-| 31|30   20|19    15|14   12|11 7|6     0| name       |
-|---|-------|--------|-------|----|-------|------------|
-| 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
-| 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
-| 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
+| 31|30   20|19    15|14..12|11 7|6     0| name       |
+|---|-------|--------|------|----|-------|------------|
+| 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
+| 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |
+| 1 | --    | --     | 111  | -- |1010111| *reserved* |
 
 
 # pseudocode