--- /dev/null
+<!-- SVP64 Butterfly DCT Instructions here described are based on -->
+
+<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
+
+# [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
+
+DCTI-Form
+
+* maddsubrs RT,RA,RB,SH
+
+Pseudo-code:
+
+ sum <- (RT) + (RA)
+ diff <- (RT) - (RA)
+ prod1 <- MUL(RB, sum)
+ prod2 <- MUL(RB, diff)
+ res1 <- ROTL64(prod1, XLEN-SH)
+ res2 <- ROTL64(prod2, XLEN-SH)
+ RT <- (RT) + res1
+ RS <- (RS) + res2
+
+Special Registers Altered:
+
+ None
fpowr,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
fpow,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
rlwimi,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
+maddsubrs,NORMAL,,1P,EXTRA3,NO,TODO,0,0,0,RT,0,RB,RT,0,CR0,0
rldimi,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
|0 |6 |11 |16 |21 |26 |31 |
| PO | FRT | FRA | FRB | // | XO | Rc |
+# 1.6.7.2 DCTI-FORM
+ |0 | 6 |11 |16 |21 |25 |31 |
+ | PO | RT | RA | RB | SH | XO | Rc |
+
# 1.6.8 XL-FORM
|0 |6 |9 |11 |14 |16 |19|20|21 |31 |
| PO | BT | BA | BB | XO | / |
| PO | FRT | FRA | FRB | FMM | XO | Rc |
| PO | RT | RA | RB | MMM | / | XO | Rc |
+
# 1.6.28 Instruction Fields
A (6)
Field used by the tbegin. instruction to specify an
RA (11:15)
Field used to specify a GPR to be used as a
source or as a target.
- Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, XB, TLI, Z23
+ Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, XB, TLI, Z23, DCTI
RB (16:20)
Field used to specify a GPR to be used as a
source.
- Formats: A, BM2, M, MDS, MM, VA, VA2, X, XO, TLI, Z23
+ Formats: A, BM2, M, MDS, MM, VA, VA2, X, XO, TLI, Z23, DCTI
Rc (21)
RECORD bit.
0 Do not alter the Condition Register.
1 Set Condition Register Field 0 or Field 1 as
described in Section 2.3.1, 'Condition Regis-
ter' on page 30.
- Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI, DCT
+ Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI, DCT, DCTI
RIC (12:13)
Field used to specify what types of entries to inval-
idate for tlbie[l].
Formats: DS, X
RT (6:10)
Field used to specify a GPR to be used as a target.
- Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, XB, TLI, Z23
+ Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, XB, TLI, Z23, DCTI
RTp (6:10)
Field used to specify an even/odd pair of GPRs to
be concatenated and used as a target.
SH (16:21)
Field used to specify a shift amount.
Formats: Z22
+ SH (21:24)
+ Field used to specify a shift amount.
+ Formats: DCTI
sh (30,16:20)
Fields that are concatenated to specify a shift
amount.
Formats: X, Z23
XO (25:30)
Extended opcode field.
- Formats: MM, TX
+ Formats: MM, TX, DCTI
XO (26:27)
Extended opcode field.
Formats: XX4
------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-----00011-,ALU,OP_FMVIS,NONE,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvis,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------01000,ALU,OP_MADDSUBRS,RT,CONST_UI,RB,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,maddsubrs,DCTI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
"fmvtg", "fmvtgs",
"fcvtfg", "fcvtfgs",
"fmvfg", "fmvfgs",
+ "maddsubrs"
]:
illegal = False
ins_name = dotstrp
--- /dev/null
+""" Decoder tests
+
+related bugs:
+
+ *
+"""
+
+import unittest
+
+from openpower.test.alu.maddsubrs_cases import MADDSUBRSTestCase
+from openpower.test.runner import TestRunnerBase
+
+# writing the test_caller invocation this way makes it work with pytest
+
+
+class TestMADDSUBRS(TestRunnerBase):
+ def __init__(self, test):
+ assert test == 'test'
+ super().__init__(MADDSUBRSTestCase().test_data)
+
+ def test(self):
+ # dummy function to make unittest try to test this class
+ pass
+
+
+if __name__ == "__main__":
+ unittest.main()
CW = 44
CW2 = 45
DCT = 46 # fdmadds
+ DCTI = 47 # maddsubrs
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
# "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
"maddedu", "maddedus",
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
+ "maddsubrs", # Integer DCT Butterfly
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
"minmax", # AV bitmanip
OP_DSHL = 101
OP_DSHR = 102
OP_SHADD = 103
+ OP_MADDSUBRS = 104
class In1Sel(Enum):
span = dict(zip(bits, range(len(bits))))
span_rev = {value:key for (key, value) in span.items()}
+ print(record)
# This part is tricky: we cannot use record.operands,
# as this code is called by record.static_operands method.
for (cls, kwargs) in record.mdwn.operands:
operand = cls(record=record, **kwargs)
+ print(operand)
+ print(operand.span)
for idx in operand.span:
+ print(idx)
rev = span.pop(idx, None)
if rev is not None:
span_rev.pop(rev, None)
--- /dev/null
+from openpower.sv.trans.svp64 import SVP64Asm
+import random
+from openpower.test.common import TestAccumulatorBase
+from openpower.endian import bigendian
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.power_enums import XER_bits
+from openpower.decoder.isa.caller import special_sprs
+from openpower.decoder.helpers import exts
+from openpower.test.state import ExpectedState
+import unittest
+
+class MADDSUBRSTestCase(TestAccumulatorBase):
+
+ def case_0_maddsubrs(self):
+ isa = SVP64Asm(["maddsubrs 1,2,3,0"])
+ lst = list(isa)
+
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x00000a70
+ initial_regs[2] = 0xffffe6b8
+ initial_regs[3] = 0x00002d41
+
+ e = ExpectedState(pc=4)
+ e.intregs[1] = 0xfffff581
+ e.intregs[11] = 0x00001942
+ self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+ self.add_case(Program(lst, bigendian), expected=e)
+
+
projects / openpower-isa.git / commitdiff