soc: Remove unused RESET_LOW generic

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
index d72b1e794ada194e7b1b7a389791f20af3973b7a..592b4f45c9840c876923dc9d495e70b98c91b4fd 100644 (file)
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@@ -61,7 +61,6 @@ begin
            SIM => true,
            MEMORY_SIZE => MEMORY_SIZE,
            RAM_INIT_FILE => MAIN_RAM_FILE,
-           RESET_LOW => false,
             HAS_DRAM => true,
            DRAM_SIZE => 256 * 1024 * 1024,
             DRAM_INIT_SIZE => ROM_SIZE,

diff --git a/core_flash_tb.vhdl b/core_flash_tb.vhdl
index 6575aa5316cf43162a293fde225cb2754680f1e0..cb19b6f121bb2f0976002f63827c831c5cdfc2c9 100644 (file)
--- a/core_flash_tb.vhdl
+++ b/core_flash_tb.vhdl
@@ -38,7 +38,6 @@ begin
            SIM => true,
            MEMORY_SIZE => (384*1024),
            RAM_INIT_FILE => "main_ram.bin",
-           RESET_LOW => false,
            CLK_FREQ => 100000000,
             HAS_SPI_FLASH    => true,
             SPI_FLASH_DLINES => 4,

diff --git a/core_tb.vhdl b/core_tb.vhdl
index ed147a3f2e3cfcb2c2234bbd622f7c27147ddecc..bf697410641040c4eff2554726e32ae14695f4e2 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -30,7 +30,6 @@ begin
            SIM => true,
            MEMORY_SIZE => (384*1024),
            RAM_INIT_FILE => "main_ram.bin",
-           RESET_LOW => false,
            CLK_FREQ => 100000000,
             HAS_SPI_FLASH => false
            )

diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index b13ed34f70ebb2e9b6a3884e09c2b6b0be2c3f42..59181e01ab7d898133d9f3eb1f48de4e00c0cba2 100644 (file)
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -128,7 +128,6 @@ begin
         generic map(
             MEMORY_SIZE        => BRAM_SIZE,
             RAM_INIT_FILE      => RAM_INIT_FILE,
-            RESET_LOW          => RESET_LOW,
             SIM                => false,
             CLK_FREQ           => CLK_FREQUENCY,
             HAS_DRAM           => USE_LITEDRAM,

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 99e7253752c4ccfc32e8b13a35a42fcf5f4c0ce2..ceaec901cbd00284d79dbaf09951f84e07ecb8e9 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -75,7 +75,6 @@ begin
        generic map(
            MEMORY_SIZE   => MEMORY_SIZE,
            RAM_INIT_FILE => RAM_INIT_FILE,
-           RESET_LOW     => RESET_LOW,
            SIM           => false,
            CLK_FREQ      => CLK_FREQUENCY,
            DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index ec78c3e3a75c0ea83e5d3728b15fa2f40705cd65..3ba22b22645f128e5586ea3771f1f87ae6067c02 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -116,7 +116,6 @@ begin
        generic map(
            MEMORY_SIZE   => BRAM_SIZE,
            RAM_INIT_FILE => RAM_INIT_FILE,
-           RESET_LOW     => RESET_LOW,
            SIM           => false,
            CLK_FREQ      => CLK_FREQUENCY,
            HAS_DRAM      => USE_LITEDRAM,

diff --git a/soc.vhdl b/soc.vhdl
index 7c8e825438929d8431dcae97405f116772007022..f1f4e4d59a7a4e39712820aeb91ccf68381d7f0e 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -30,7 +30,6 @@ entity soc is
     generic (
        MEMORY_SIZE        : natural;
        RAM_INIT_FILE      : string;
-       RESET_LOW          : boolean;
        CLK_FREQ           : positive;
        SIM                : boolean;
        DISABLE_FLATTEN_CORE : boolean := false;