r600g: implement ISSG on r600-evergreen

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index d34f3a52fcb59a9ee6d086371a1e4219c7be4bc5..96eb3babb514edf54cf451aacb9607c4a54a7614 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1983,6 +1983,67 @@ static int tgsi_iabs(struct r600_shader_ctx *ctx)
        return 0;
 }
 
+static int tgsi_issg(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int i, r;
+       unsigned write_mask = inst->Dst[0].Register.WriteMask;
+       int last_inst = tgsi_last_instruction(write_mask);
+
+       /* tmp = (src >= 0 ? src : -1) */
+       for (i = 0; i < 4; i++) {
+               if (!(write_mask & (1<<i)))
+                       continue;
+
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+               alu.is_op3 = 1;
+
+               alu.dst.sel = ctx->temp_reg;
+               alu.dst.chan = i;
+               alu.dst.write = 1;
+
+               r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+               r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
+               alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
+
+               if (i == last_inst)
+                       alu.last = 1;
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+
+       /* dst = (tmp > 0 ? 1 : tmp) */
+       for (i = 0; i < 4; i++) {
+               if (!(write_mask & (1<<i)))
+                       continue;
+
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
+               alu.is_op3 = 1;
+               alu.dst.write = 1;
+
+               tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+
+               alu.src[0].sel = ctx->temp_reg;
+               alu.src[0].chan = i;
+
+               alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
+
+               alu.src[2].sel = ctx->temp_reg;
+               alu.src[2].chan = i;
+
+               if (i == last_inst)
+                       alu.last = 1;
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+       return 0;
+}
+
 
 
 static int tgsi_ssg(struct r600_shader_ctx *ctx)
@@ -3774,6 +3835,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UARL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
        {TGSI_OPCODE_UCMP,      0, 0, tgsi_unsupported},
        {TGSI_OPCODE_IABS,      0, 0, tgsi_iabs},
+       {TGSI_OPCODE_ISSG,      0, 0, tgsi_issg},
        {TGSI_OPCODE_LAST,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 };
 
@@ -3947,6 +4009,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UARL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
        {TGSI_OPCODE_UCMP,      0, 0, tgsi_unsupported},
        {TGSI_OPCODE_IABS,      0, 0, tgsi_iabs},
+       {TGSI_OPCODE_ISSG,      0, 0, tgsi_issg},
        {TGSI_OPCODE_LAST,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 };