Get rid of sigPused

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 4d2152f61275b9b671cdd58aa16dad6c69b86427..0d1937844cd8b66c0856d05e0e53f3f19c22564f 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -43,8 +43,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
        log("postAdd:    %s\n", log_id(st.postAdd, "--"));
        log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
        log("ffP:        %s\n", log_id(st.ffP, "--"));
-       //log("muxP:  %s\n", log_id(st.muxP, "--"));
-       log("sigPused:   %s\n", log_signal(st.sigPused));
 #endif
 
        log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index c45e92d6f885e90b9e447d8bb5608e424ed2d63a..375b5a492681aba5d200233738e3d392fb49777c 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -19,8 +19,16 @@ code sigAset sigBset
 endcode
 
 code sigM
-       sigM = port(dsp, \P);
-       //if (GetSize(sigH) <= 10)
+       SigSpec P = port(dsp, \P);
+       // Only care about those bits that are used
+       int i;
+       for (i = 0; i < GetSize(P); i++) {
+               if (nusers(P[i]) <= 1)
+                       break;
+               sigM.append(P[i]);
+       }
+       log_assert(nusers(P.extract_end(i)) <= 1);
+       //if (GetSize(sigM) <= 10)
        //      reject;
 endcode
 
@@ -156,23 +164,14 @@ code sigC sigP
        }
 endcode
 
-// Extract the bits of P that actually have a consumer
-// (as opposed to being a dummy)
-code sigPused
-       for (int i = 0; i < GetSize(sigP); i++)
-               if (sigP[i].wire && nusers(sigP[i]) > 1)
-                       sigPused.append(sigP[i]);
-endcode
-
 match ffP
        if param(dsp, \PREG).as_int() == 0
-       if !sigPused.empty()
-       if nusers(sigPused) == 2
        select ffP->type.in($dff)
        // DSP48E1 does not support clock inversion
        select param(ffP, \CLK_POLARITY).as_bool()
-       filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
-       filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
+       filter GetSize(port(ffP, \D)) >= GetSize(sigP)
+       slice offset GetSize(port(ffP, \D))
+       filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
        optional
 endmatch