---------- Begin Simulation Statistics ----------
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 728920000 # Number of ticks simulated
-final_tick 728920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000731 # Number of seconds simulated
+sim_ticks 731328000 # Number of ticks simulated
+final_tick 731328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1560894 # Simulator instruction rate (inst/s)
-host_op_rate 1560871 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 568880584 # Simulator tick rate (ticks/s)
-host_mem_usage 223172 # Number of bytes of host memory used
-host_seconds 1.28 # Real time elapsed on the host
-sim_insts 1999954 # Number of instructions simulated
-sim_ops 1999954 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3428 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 300982275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 141535422 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 300982275 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 1393062 # Simulator instruction rate (inst/s)
+host_op_rate 1393035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 509417209 # Simulator tick rate (ticks/s)
+host_mem_usage 231840 # Number of bytes of host memory used
+host_seconds 1.44 # Real time elapsed on the host
+sim_insts 1999829 # Number of instructions simulated
+sim_ops 1999829 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 299991249 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141069397 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 299991249 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1457840 # number of cpu cycles simulated
+system.cpu0.numCycles 1462656 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu0.num_busy_cycles 1462656 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 216.308996 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 216.390931 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.422639 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.422639 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 216.308996 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.422479 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.422479 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 23474000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 23474000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23730000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 23730000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 23730000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 23730000 # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::total 23730000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50699.784017 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
+system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51252.699784 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51252.699784 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51252.699784 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51252.699784 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22085000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22085000 # number of overall MSHR miss cycles
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+system.cpu0.icache.ReadReq_mshr_miss_latency::total 22341000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22341000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 22341000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22341000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 22341000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average ReadReq mshr miss latency
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+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 273.374896 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 273.518805 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.534216 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.534216 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 17785000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 25578000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 25578000 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 54891.975309 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56064.748201 # average WriteReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55244.060475 # average overall miss latency
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 55055.555556 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 55055.555556 # average ReadReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 55466.522678 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24189000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 24189000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16866000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16866000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7426000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7426000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24292000 # number of demand (read+write) MSHR miss cycles
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff