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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 09fa4629339481a958e163fa4e0c2b7c69bebe04..2638f648f5036bbc516eb8ef3a4ee7cb72e04f44 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -848,6 +848,18 @@ CPU as a software-extension: PEs generate a TLB Miss notification
 to the main CPU over OpenCAPI, and the main CPU feeds back the new
 TLB entries to the PE in response.
 
+Also in practical terms, with the PEs anticipated to be so small as to
+make running a full SMP-aware OS impractical it will not just be their TLB
+pages that need remote management but their entire register file including
+the Program Counter will need to be set up, and the ZOLC Context as
+well. With OpenCAPI packet formats being quite large a concern is that
+the context management increases latency to the point where the premise
+of this paper is invalidated. Research is needed here as to whether a
+bare-bones microkernel
+would be viable, or a Management Core closer to the PEs (on the same
+die or Multi-Chip-Module as the PEs) would allow better bandwidth and
+reduce Management Overhead on the main CPUs.
+
 **Use-case: Matrix and Convolutions**
 
 * **Horizontal-First**: (aka standard Cray Vectors) walk