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power_insn: disassemble RA0 and RT0 correctly
authorDmitry Selyutin <ghostmansd@gmail.com>
Wed, 31 May 2023 21:05:08 +0000 (00:05 +0300)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:19 +0000 (19:51 +0100)
src/openpower/decoder/power_insn.py patch | blob | history

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index d480a3f3dac4073743c1b32cff8451d970a2057c..ca540386560906d0c6a538f648fa793741b714ce 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1286,6 +1286,9 @@ class ExtendableOperand(DynamicOperand):
             style=Style.NORMAL, prefix="", indent=""):
         (vector, value, span) = self.sv_spec(insn=insn)
 
+        if (self.extra_reg.or_zero and (value == 0)):
+            prefix = ""
+
         if style >= Style.VERBOSE:
             mode = "vector" if vector else "scalar"
             yield f"{indent}{self.name} ({mode})"