[ARM] Use proper output modifier for DImode register in store exclusive patterns

	* config/arm/sync.md (arm_store_exclusive<mode>):
	Use 'H' output modifier on operands[2] rather than creating a new
	entry in out-of-bounds memory of the operands array.
	(arm_store_release_exclusivedi): Likewise.

From-SVN: r236984

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b9baf4c9c0a85c9cacc1f0061baad4d2ef1d39ef..0bb7f286c8ed104cb9a4bf3a68dd99d49e5ed73f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/sync.md (arm_store_exclusive<mode>):
+       Use 'H' output modifier on operands[2] rather than creating a new
+       entry in out-of-bounds memory of the operands array.
+       (arm_store_release_exclusivedi): Likewise.
+
 2016-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/arm/arm.c (arm_fusion_enabled_p): New function.

diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 0589e4d89059bd0845e5c4741516f04a567459a7..abcfbcb1eacaabc597c9fde475c1b56624fb5a59 100644 (file)
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -452,14 +452,13 @@
   {
     if (<MODE>mode == DImode)
       {
-       rtx value = operands[2];
        /* The restrictions on target registers in ARM mode are that the two
           registers are consecutive and the first one is even; Thumb is
           actually more flexible, but DI should give us this anyway.
-          Note that the 1st register always gets the lowest word in memory.  */
-       gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
-       operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
-       return "strexd%?\t%0, %2, %3, %C1";
+          Note that the 1st register always gets the
+          lowest word in memory.  */
+       gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
+       return "strexd%?\t%0, %2, %H2, %C1";
       }
     return "strex<sync_sfx>%?\t%0, %2, %C1";
   }
@@ -475,11 +474,9 @@
          VUNSPEC_SLX))]
   "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
   {
-    rtx value = operands[2];
     /* See comment in arm_store_exclusive<mode> above.  */
-    gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
-    operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
-    return "stlexd%?\t%0, %2, %3, %C1";
+    gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
+    return "stlexd%?\t%0, %2, %H2, %C1";
   }
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")])