Cache: Collect very basic stats on tag and data accesses

Adds very basic statistics on the number of tag and data accesses within the
cache, which is important for power modelling.  For the tags, simply count
the associativity of the cache each time.  For the data, this depends on
whether tags and data are accessed sequentially, which is given by a new
parameter.  In the parallel case, all data blocks are accessed each time, but
with sequential accesses, a single data block is accessed only on a hit.

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index df4602199aac5cc2694f49e611159bf0b508a571..9ffe399817e5e99e4ea822a7b5b9d6026f2ed8fa 100644 (file)
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -69,4 +69,6 @@ class BaseCache(MemObject):
     mem_side = MasterPort("Port on side closer to MEM")
     addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")
+    sequential_access = Param.Bool(False,
+        "Whether to access tags and data sequentially")
     tags = Param.BaseTags(LRU(), "Tag Store for LRU caches")

diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index c5beff4a78384d81937e4d84e05af6d77efe88ef..7c0dded32a3a53461c3eb42e22c6cfcf889d9057 100644 (file)
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -58,6 +58,8 @@ class LRU(BaseTags):
     cxx_class = 'LRU'
     cxx_header = "mem/cache/tags/lru.hh"
     assoc = Param.Int(Parent.assoc, "associativity")
+    sequential_access = Param.Bool(Parent.sequential_access,
+        "Whether to access tags and data sequentially")
 
 class FALRU(BaseTags):
     type = 'FALRU'

diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index b669a5b06491dd5b1771ca3a63532eca4f51a53b..446c1ea49a6b5af33f1c2dca60d8d4dd15d0ac62 100644 (file)
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -147,6 +147,16 @@ BaseTags::regStats()
 
     percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
 
+    tagAccesses
+        .name(name() + ".tag_accesses")
+        .desc("Number of tag accesses")
+        ;
+
+    dataAccesses
+        .name(name() + ".data_accesses")
+        .desc("Number of data accesses")
+        ;
+
     registerDumpCallback(new BaseTagsDumpCallback(this));
     registerExitCallback(new BaseTagsCallback(this));
 }

diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index e8c71f01f858cdffe1a96e85834ed947c0f9df17..9e1fb197219af26edbbdd26589589923efb63ae2 100644 (file)
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -130,6 +130,11 @@ class BaseTags : public ClockedObject
     /** Occ % of each context/cpu using the cache */
     Stats::Formula percentOccsTaskId;
 
+    /** Number of tags consulted over all accesses. */
+    Stats::Scalar tagAccesses;
+    /** Number of data blocks consulted over all accesses. */
+    Stats::Scalar dataAccesses;
+
     /**
      * @}
      */

diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 6b05744af08aa0b00efa1007be0edf0de7c3e2ff..58f3f097706a1e43dc19ddf743f1ef1f82786f95 100644 (file)
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -58,7 +58,8 @@ using namespace std;
 
 LRU::LRU(const Params *p)
     :BaseTags(p), assoc(p->assoc),
-     numSets(p->size / (p->block_size * p->assoc))
+     numSets(p->size / (p->block_size * p->assoc)),
+     sequentialAccess(p->sequential_access)
 {
     // Check parameters
     if (blkSize < 4 || !isPowerOf2(blkSize)) {
@@ -132,6 +133,19 @@ LRU::accessBlock(Addr addr, Cycles &lat, int master_id)
     unsigned set = extractSet(addr);
     BlkType *blk = sets[set].findBlk(tag);
     lat = hitLatency;
+
+    // Access all tags in parallel, hence one in each way.  The data side
+    // either accesses all blocks in parallel, or one block sequentially on
+    // a hit.  Sequential access with a miss doesn't access data.
+    tagAccesses += assoc;
+    if (sequentialAccess) {
+        if (blk != NULL) {
+            dataAccesses += 1;
+        }
+    } else {
+        dataAccesses += assoc;
+    }
+
     if (blk != NULL) {
         // move this block to head of the MRU list
         sets[set].moveToHead(blk);
@@ -216,6 +230,10 @@ LRU::insertBlock(PacketPtr pkt, BlkType *blk)
 
     unsigned set = extractSet(addr);
     sets[set].moveToHead(blk);
+
+    // We only need to write into one tag and one data block.
+    tagAccesses += 1;
+    dataAccesses += 1;
 }
 
 void

diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 68c29b754f7548cba2371bd10fedeb28bcae6333..b9f8fc25c7271d192abff98a935f39cb962a6352 100644 (file)
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -81,6 +81,8 @@ class LRU : public BaseTags
     const unsigned assoc;
     /** The number of sets in the cache. */
     const unsigned numSets;
+    /** Whether tags and data are accessed sequentially. */
+    const bool sequentialAccess;
 
     /** The cache sets. */
     SetType *sets;