machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.

diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v
index 054b678b34c82f1bca838284e26250dc77ec6fed..924df6f25553177a49f7b8d6c3557a9aae748580 100644 (file)
--- a/techlibs/machxo2/cells_map.v
+++ b/techlibs/machxo2/cells_map.v
@@ -17,11 +17,11 @@ module \$lut (A, Y);
                end else if(WIDTH == 4) begin
                        assign I = {A[3], A[2], A[1], A[0]};
                end else begin
-                       INVALID_LUT_WIDTH error();
+                       wire _TECHMAP_FAIL_ = 1;
                end
        endgenerate
 
-       LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .F(Y));
+       LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
 endmodule
 
 module  \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule

diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 8db73c50c77aff9683afa3e8d82bd3ed9521d141..2c4d2f462735e5d935e2ed4181731183cf306ed3 100644 (file)
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -2,7 +2,7 @@ module LUT4 #(
        parameter [15:0] INIT = 0
 ) (
        input A, B, C, D,
-       output F
+       output Z
 );
        wire [3:0] I;
        wire [3:0] I_pd;
@@ -14,7 +14,7 @@ module LUT4 #(
        endgenerate
 
        assign I = {D, C, B, A};
-       assign F = INIT[I_pd];
+       assign Z = INIT[I_pd];
 endmodule
 
 module FACADE_FF #(