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AVX-512. Add pd2dq and dq2pd converts.
authorAlexander Ivchenko <alexander.ivchenko@intel.com>
Thu, 25 Sep 2014 08:15:30 +0000 (08:15 +0000)
committerKirill Yukhin <kyukhin@gcc.gnu.org>
Thu, 25 Sep 2014 08:15:30 +0000 (08:15 +0000)
gcc/
* config/i386/i386.c
(avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ...
(ufix_notruncv8dfv8si2_mask_round): ... this.
* config/i386/sse.md
(define_insn "avx512f_cvtdq2pd512_2): Update TARGET check.
(define_insn "avx_cvtdq2pd256_2"): Add EVEX version.
(define_insn "sse2_cvtdq2pd<mask_name>"): Add masking.
(define_insn "avx_cvtpd2dq256<mask_name>"): Ditto.
(define_expand "sse2_cvtpd2dq"): Delete.
(define_insn "sse2_cvtpd2dq<mask_name>"): Add masking and
make 2nd operand const0 vector.
(define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"):
Delete.
(define_mode_attr pd2udqsuff): New.
(define_insn
"ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"): Ditto.
(define_insn "ufix_notruncv2dfv2si2<mask_name>"): Ditto.
(define_insn "*avx_cvttpd2dq256_2"): Delete.
(define_expand "sse2_cvttpd2dq"): Ditto.
(define_insn "sse2_cvttpd2dq<mask_name>"): Add masking and
make 2nd operand const0 vector.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r215584

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.c patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d1ae0a428e65bc588c2f85dfc259f72be279f013..e7a932f274bd6d080551e436fd684d3a6276f89f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,34 @@
+2014-09-25  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/i386.c
+       (avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ...
+       (ufix_notruncv8dfv8si2_mask_round): ... this.
+       * config/i386/sse.md
+       (define_insn "avx512f_cvtdq2pd512_2): Update TARGET check.
+       (define_insn "avx_cvtdq2pd256_2"): Add EVEX version.
+       (define_insn "sse2_cvtdq2pd<mask_name>"): Add masking.
+       (define_insn "avx_cvtpd2dq256<mask_name>"): Ditto.
+       (define_expand "sse2_cvtpd2dq"): Delete.
+       (define_insn "sse2_cvtpd2dq<mask_name>"): Add masking and
+       make 2nd operand const0 vector.
+       (define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"):
+       Delete.
+       (define_mode_attr pd2udqsuff): New.
+       (define_insn
+       "ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"): Ditto.
+       (define_insn "ufix_notruncv2dfv2si2<mask_name>"): Ditto.
+       (define_insn "*avx_cvttpd2dq256_2"): Delete.
+       (define_expand "sse2_cvttpd2dq"): Ditto.
+       (define_insn "sse2_cvttpd2dq<mask_name>"): Add masking and
+       make 2nd operand const0 vector.
+
 2014-09-25  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/63341
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d70420d4814d1eb58d1e55f8ca0de1df1682f9c8..1aec70fe4ce855b3c46845d17bc2dd2dd5d3ca2f 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -30246,7 +30246,7 @@ static const struct builtin_description bdesc_round_args[] =
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round,  "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
-  { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
+  { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round,  "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
   { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 287fd115e11096b0b8644458f712230511234d33..b2e1d4fa6db094162efe7ab4ebb73bb89c3be091 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4463,33 +4463,33 @@
                       (const_int 2) (const_int 3)
                       (const_int 4) (const_int 5)
                       (const_int 6) (const_int 7)]))))]
-  "TARGET_AVX"
+  "TARGET_AVX512F"
   "vcvtdq2pd\t{%t1, %0|%0, %t1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "evex")
    (set_attr "mode" "V8DF")])
 
 (define_insn "avx_cvtdq2pd256_2"
-  [(set (match_operand:V4DF 0 "register_operand" "=x")
+  [(set (match_operand:V4DF 0 "register_operand" "=v")
        (float:V4DF
          (vec_select:V4SI
-           (match_operand:V8SI 1 "nonimmediate_operand" "xm")
+           (match_operand:V8SI 1 "nonimmediate_operand" "vm")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)]))))]
   "TARGET_AVX"
   "vcvtdq2pd\t{%x1, %0|%0, %x1}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "V4DF")])
 
-(define_insn "sse2_cvtdq2pd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x")
+(define_insn "sse2_cvtdq2pd<mask_name>"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
        (float:V2DF
          (vec_select:V2SI
-           (match_operand:V4SI 1 "nonimmediate_operand" "xm")
+           (match_operand:V4SI 1 "nonimmediate_operand" "vm")
            (parallel [(const_int 0) (const_int 1)]))))]
-  "TARGET_SSE2"
-  "%vcvtdq2pd\t{%1, %0|%0, %q1}"
+  "TARGET_SSE2 && <mask_avx512vl_condition>"
+  "%vcvtdq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "ssememalign" "64")
@@ -4506,14 +4506,14 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "OI")])
 
-(define_insn "avx_cvtpd2dq256"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
-       (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
+(define_insn "avx_cvtpd2dq256<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+       (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
                     UNSPEC_FIX_NOTRUNC))]
-  "TARGET_AVX"
-  "vcvtpd2dq{y}\t{%1, %0|%0, %1}"
+  "TARGET_AVX && <mask_avx512vl_condition>"
+  "vcvtpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "<mask_prefix>")
    (set_attr "mode" "OI")])
 
 (define_expand "avx_cvtpd2dq256_2"
@@ -4538,25 +4538,16 @@
    (set_attr "btver2_decode" "vector")
    (set_attr "mode" "OI")])
 
-(define_expand "sse2_cvtpd2dq"
-  [(set (match_operand:V4SI 0 "register_operand")
-       (vec_concat:V4SI
-         (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")]
-                      UNSPEC_FIX_NOTRUNC)
-         (match_dup 2)))]
-  "TARGET_SSE2"
-  "operands[2] = CONST0_RTX (V2SImode);")
-
-(define_insn "*sse2_cvtpd2dq"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
+(define_insn "sse2_cvtpd2dq<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
        (vec_concat:V4SI
-         (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
+         (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
                       UNSPEC_FIX_NOTRUNC)
-         (match_operand:V2SI 2 "const0_operand")))]
-  "TARGET_SSE2"
+         (const_vector:V2SI [(const_int 0) (const_int 0)])))]
+  "TARGET_SSE2 && <mask_avx512vl_condition>"
 {
   if (TARGET_AVX)
-    return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
+    return "vcvtpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
   else
     return "cvtpd2dq\t{%1, %0|%0, %1}";
 }
@@ -4569,16 +4560,33 @@
    (set_attr "athlon_decode" "vector")
    (set_attr "bdver1_decode" "double")])
 
-(define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"
-  [(set (match_operand:V8SI 0 "register_operand" "=v")
-       (unspec:V8SI
-         [(match_operand:V8DF 1 "<round_nimm_predicate>" "<round_constraint>")]
+;; For ufix_notrunc* insn patterns
+(define_mode_attr pd2udqsuff
+  [(V8DF "") (V4DF "{y}")])
+
+(define_insn "ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"
+  [(set (match_operand:<si2dfmode> 0 "register_operand" "=v")
+       (unspec:<si2dfmode>
+         [(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "<round_constraint>")]
          UNSPEC_UNSIGNED_FIX_NOTRUNC))]
   "TARGET_AVX512F"
-  "vcvtpd2udq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+  "vcvtpd2udq<pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "evex")
-   (set_attr "mode" "OI")])
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "ufix_notruncv2dfv2si2<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+       (vec_concat:V4SI
+         (unspec:V2SI
+           [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
+           UNSPEC_UNSIGNED_FIX_NOTRUNC)
+         (const_vector:V2SI [(const_int 0) (const_int 0)])))]
+  "TARGET_AVX512VL"
+  "vcvtpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "TI")])
 
 (define_insn "<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>"
   [(set (match_operand:V8SI 0 "register_operand" "=v")
@@ -4659,35 +4667,15 @@
   "TARGET_AVX"
   "operands[2] = CONST0_RTX (V4SImode);")
 
-(define_insn "*avx_cvttpd2dq256_2"
-  [(set (match_operand:V8SI 0 "register_operand" "=x")
-       (vec_concat:V8SI
-         (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm"))
-         (match_operand:V4SI 2 "const0_operand")))]
-  "TARGET_AVX"
-  "vcvttpd2dq{y}\t{%1, %x0|%x0, %1}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
-   (set_attr "btver2_decode" "vector")
-   (set_attr "mode" "OI")])
-
-(define_expand "sse2_cvttpd2dq"
-  [(set (match_operand:V4SI 0 "register_operand")
-       (vec_concat:V4SI
-         (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand"))
-         (match_dup 2)))]
-  "TARGET_SSE2"
-  "operands[2] = CONST0_RTX (V2SImode);")
-
-(define_insn "*sse2_cvttpd2dq"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
+(define_insn "sse2_cvttpd2dq<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
        (vec_concat:V4SI
-         (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
-         (match_operand:V2SI 2 "const0_operand")))]
-  "TARGET_SSE2"
+         (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
+         (const_vector:V2SI [(const_int 0) (const_int 0)])))]
+  "TARGET_SSE2 && <mask_avx512vl_condition>"
 {
   if (TARGET_AVX)
-    return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
+    return "vcvttpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
   else
     return "cvttpd2dq\t{%1, %0|%0, %1}";
 }