add stb signal

diff --git a/miscope/mila.py b/miscope/mila.py
index 9596cbd115f9635eed8fb9934d2e5b3f2579f5f2..7286e4ee3315c8ed753b1d2add532d92b2143439 100644 (file)
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -12,8 +12,9 @@ class MiLa:
                self.recorder = recorder
                self.interface = interface
                
-               self.trig = Signal(self.trigger.trig_w)
-               self.dat  = Signal(self.trigger.trig_w)
+               self.stb = Signal(reset=1)
+               self.trig = Signal(self.trigger.width)
+               self.dat  = Signal(self.recorder.width)
                
                self.set_address(address)
                self.set_interface(interface)
@@ -30,6 +31,7 @@ class MiLa:
                
        def get_fragment(self):
                comb =[
+                       self.recorder.stb.eq(self.stb),
                        self.trigger.trig.eq(self.trig),
                        
                        self.recorder.dat.eq(self.dat),

diff --git a/miscope/recorder.py b/miscope/recorder.py
index 7eb0a8a7a48602c2fca7266fc5cbef09ca8211eb..ee7e3aa0fc76f67d07f1721a03b01bfbaf3d92b4 100644 (file)
--- a/miscope/recorder.py
+++ b/miscope/recorder.py
@@ -94,6 +94,7 @@ class RLE:
                self.enable = Signal()
 
                # Input
+               self.stb_i = Signal()
                self.dat_i = Signal(width)
 
                # Output
@@ -102,14 +103,16 @@ class RLE:
                
        def get_fragment(self):
 
-               # Register Input                
+               # Register Input
+               stb_i_d = Signal()
                dat_i_d = Signal(self.width)
 
                sync =[dat_i_d.eq(self.dat_i)]
-
+               sync +=[stb_i_d.eq(self.stb_i)]
+               
                # Detect diff
                diff = Signal()
-               comb = [diff.eq(~self.enable | (dat_i_d != self.dat_i))]
+               comb = [diff.eq(self.stb_i & (~self.enable | (dat_i_d != self.dat_i)))]
 
                diff_rising = RisingEdge(diff)
                diff_d = Signal()
@@ -136,7 +139,7 @@ class RLE:
                                self.dat_o[self.width-1].eq(1),
                                self.dat_o[:len(rle_cnt)].eq(rle_cnt)
                        ).Elif(diff_d | rle_max,
-                               self.stb_o.eq(1),
+                               self.stb_o.eq(stb_i_d),
                                self.dat_o.eq(dat_i_d)
                        ).Else(
                                self.stb_o.eq(0),
@@ -236,6 +239,7 @@ class Recorder:
                
                # trigger Interface
                self.hit = Signal()
+               self.stb = Signal()
                self.dat = Signal(self.width)
        
        def set_address(self, address):
@@ -271,6 +275,7 @@ class Recorder:
                        self.sequencer.done.eq(self.storage.done),
                        self.sequencer.hit.eq(self.hit),
                        
+                       self.rle.stb_i.eq(self.stb),
                        self.rle.dat_i.eq(self.dat),
 
                        self.storage.push_stb.eq(self.sequencer.enable & self.rle.stb_o),

diff --git a/miscope/trigger.py b/miscope/trigger.py
index 04013c2a5f55c022f74338c2860544bc5021782a..59f5f60427f338ff2ad0b5d4a5fca3ffea26e0b3 100644 (file)
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -227,7 +227,7 @@ class Sum:
                                self._prog_port.we.eq(self.prog_stb),
                                self._prog_port.dat_w.eq(self.prog_dat),
 
-                               self.o.eq(self._lut_port.dat_r),                                
+                               self.o.eq(self._lut_port.dat_r),
                ]
                comb += self.get_registers_comb()
                return Fragment(comb, specials={self._mem})
@@ -248,12 +248,12 @@ class Trigger:
        # 
        # Definition
        #
-       def __init__(self, trig_w, ports, address=0x0000, interface=None):
-               self.trig_w = trig_w
+       def __init__(self, width, ports, address=0x0000, interface=None):
+               self.width = width
                self.ports = ports
                
                self.sum = Sum(len(ports))
-               self.trig = Signal(self.trig_w)
+               self.trig = Signal(self.width)
                self.hit = Signal()
                
                # insert port number in port reg name