(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 44ee7ad56c6bf124a4d1306cb6c3fd456300c6e1..52e98cee01363d01a81774607113e70301e240e9 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -8,6 +8,7 @@ See links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=535>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
+* <https://bugs.libre-soc.org/show_bug.cgi?id=862> VF Predication
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * [[sv/svstep]]
 * pseudocode [[openpower/isa/simplev]]
@@ -176,6 +177,8 @@ because Vertical-First is not that different from executing standard
 Scalar instructions,
 a simple branch-conditional test should be used instead of predication,
 exactly as would normally be done if SVP64 was not in use.
+Alternatively the `setvl` instruction may be called again with the `vf`
+flag set. This tells the hardware to re-assess the use of Predicates
 
 These rules allow Hardware implementors to choose to
 free up the connection