soc/cores/sdram/settings: simplify modules and fix timing margins computation

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 790c69fe2592d8ce16ab4a8be6011f9ab5c03fb2..c0a4c6ddb79eacf726a68bfd4961f1c4f09cafe8 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -95,8 +95,8 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
-            sdram_module = IS42S16160(self.clk_freq)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
+            sdram_module = IS42S16160(self.clk_freq, "1:1")
             self.register_sdram(self.sdrphy, "minicon",
                                 sdram_module.geom_settings, sdram_module.timing_settings)
 

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index b63a9fc8d9f99efcb3d890eff2084318c83273bf..a77f6f95805b3f0ba5bc431aa5da6f9b309aebca 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
 
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
-            sdram_module = MT8JTF12864(self.clk_freq)
+            sdram_module = MT8JTF12864(self.clk_freq, "1:4")
             self.register_sdram(self.ddrphy, sdram_controller_type,
                                 sdram_module.geom_settings, sdram_module.timing_settings)
 

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 7fead6956c79db574c37fde0e7354f7a4fdb3fe8..19df78abf878758b2cd091e874076a8d0264d85f 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -76,7 +76,7 @@ class BaseSoC(SoCSDRAM):
 
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
-            sdram_module = AS4C16M16(clk_freq)
+            sdram_module = AS4C16M16(clk_freq, "1:1")
             self.register_sdram(self.sdrphy, "minicon",
                                 sdram_module.geom_settings, sdram_module.timing_settings)
 

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 8c0f17c5de28a5c506c238e25b46c0984d9ce863..c6d972e2cdddd96bcd0b1dba4cbf09547f8d695c 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -31,7 +31,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.uart = uart.UART(self.uart_phy)
 
         if not self.integrated_main_ram_size:
-            sdram_module = IS42S16160(self.clk_freq)
+            sdram_module = IS42S16160(self.clk_freq, "1:1")
             phy_settings = PhySettings(
                 memtype="SDR",
                 dfi_databits=1*16,

diff --git a/litex/soc/cores/sdram/settings.py b/litex/soc/cores/sdram/settings.py
index 0e99ac12c8d2548a07b503044f7ced4e8e4e7b0b..6f61d1be5a308ac59ff2297edc772f506a1622bc 100644 (file)
--- a/litex/soc/cores/sdram/settings.py
+++ b/litex/soc/cores/sdram/settings.py
@@ -27,204 +27,170 @@ TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
 
 
 class SDRAMModule:
-    def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
+    def __init__(self, clk_freq, rate):
         self.clk_freq = clk_freq
-        self.memtype = memtype
+        self.rate = rate
         self.geom_settings = GeomSettings(
-            bankbits=log2_int(geom_settings["nbanks"]),
-            rowbits=log2_int(geom_settings["nrows"]),
-            colbits=log2_int(geom_settings["ncols"]),
+            bankbits=log2_int(self.nbanks),
+            rowbits=log2_int(self.nrows),
+            colbits=log2_int(self.ncols),
         )
         self.timing_settings = TimingSettings(
-            tRP=self.ns(timing_settings["tRP"]),
-            tRCD=self.ns(timing_settings["tRCD"]),
-            tWR=self.ns(timing_settings["tWR"]),
-            tWTR=timing_settings["tWTR"],
-            tREFI=self.ns(timing_settings["tREFI"], False),
-            tRFC=self.ns(timing_settings["tRFC"])
+            tRP=self.ns(self.tRP),
+            tRCD=self.ns(self.tRCD),
+            tWR=self.ns(self.tWR),
+            tWTR=self.tWTR,
+            tREFI=self.ns(self.tREFI, False),
+            tRFC=self.ns(self.tRFC)
         )
 
     def ns(self, t, margin=True):
         clk_period_ns = 1000000000/self.clk_freq
         if margin:
-            t += clk_period_ns/2
+            margins = {
+                "1:1" : 0,
+                "1:2" : clk_period_ns/2,
+                "1:4" : 3*clk_period_ns/4
+            }
+            t += margins[self.rate]
         return ceil(t/clk_period_ns)
 
 
 # SDR
 class IS42S16160(SDRAMModule):
-    geom_settings = {
-        "nbanks": 4,
-        "nrows":  8192,
-        "ncols":  512
-    }
-    # Timings for -7 speedgrade
-    timing_settings = {
-        "tRP":   20,
-        "tRCD":  20,
-        "tWR":   20,
-        "tWTR":  2,
-        "tREFI": 64*1000*1000/8192,
-        "tRFC":  70
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
-            self.timing_settings)
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 512
+    # timings (-7 speedgrade)
+    tRP   = 20
+    tRCD  = 20
+    tWR   = 20
+    tWTR  = 2
+    tREFI = 64*1000*1000/8192
+    tRFC  = 70
 
 
 class MT48LC4M16(SDRAMModule):
-    geom_settings = {
-        "nbanks": 4,
-        "nrows":  4096,
-        "ncols":  256
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   14,
-        "tWTR":  2,
-        "tREFI": 64*1000*1000/4096,
-        "tRFC":  66
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
-            self.timing_settings)
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 4096
+    ncols  = 256
+    # timings (-7 speedgrade)
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 14
+    tWTR  = 2
+    tREFI = 64*1000*1000/4096
+    tRFC  = 66
 
 
 class AS4C16M16(SDRAMModule):
-    geom_settings = {
-        "nbanks": 4,
-        "nrows":  8192,
-        "ncols":  512
-    }
-    # Timings for -6 speedgrade
-    timing_settings = {
-        "tRP":   18,
-        "tRCD":  18,
-        "tWR":   12,
-        "tWTR":  2,
-        "tREFI": 64*1000*1000/8192,
-        "tRFC":  60
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
-            self.timing_settings)
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 512
+    # timings (-6 speedgrade)
+    tRP   = 18
+    tRCD  = 18
+    tWR   = 12
+    tWTR  = 2
+    tREFI = 64*1000*1000/8192
+    tRFC  = 60
 
 
 # DDR
 class MT46V32M16(SDRAMModule):
-    geom_settings = {
-        "nbanks": 4,
-        "nrows":  8192,
-        "ncols":  1024
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   15,
-        "tWTR":  2,
-        "tREFI": 64*1000*1000/8192,
-        "tRFC":  70
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
-            self.timing_settings)
+    memtype = "DDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings (-6 speedgrade)
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 2
+    tREFI = 64*1000*1000/8192
+    tRFC  = 70
 
 
 # LPDDR
 class MT46H32M16(SDRAMModule):
-    geom_settings = {
-        "nbanks": 4,
-        "nrows":  8192,
-        "ncols":  1024
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   15,
-        "tWTR":  2,
-        "tREFI": 64*1000*1000/8192,
-        "tRFC":  72
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
-            self.timing_settings)
+    memtype = "LPDDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 2
+    tREFI = 64*1000*1000/8192
+    tRFC  = 72
 
 
 # DDR2
 class MT47H128M8(SDRAMModule):
-    geom_settings = {
-        "nbanks": 8,
-        "nrows":  16384,
-        "ncols":  1024
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   15,
-        "tWTR":  2,
-        "tREFI": 7800,
-        "tRFC":  127.5
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
-            self.timing_settings)
+    memtype = "DDR2"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 2
+    tREFI = 7800
+    tRFC  = 127.5
 
 
 class P3R1GE4JGF(SDRAMModule):
-    geom_settings = {
-        "nbanks": 8,
-        "nrows": 8192,
-        "ncols": 1024
-    }
-    timing_settings = {
-        "tRP":   12.5,
-        "tRCD":  12.5,
-        "tWR":   15,
-        "tWTR":  3,
-        "tREFI": 7800,
-        "tRFC":  127.5,
-    }
-
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
-            self.timing_settings)
+    memtype = "DDR2"
+    # geometry
+    nbanks = 8
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    tRP   = 12.5
+    tRCD  = 12.5
+    tWR   = 15
+    tWTR  = 3
+    tREFI = 7800
+    tRFC  = 127.5
 
 
 # DDR3
 class MT8JTF12864(SDRAMModule):
-    geom_settings = {
-        "nbanks": 8,
-        "nrows":  16384,
-        "ncols":  1024
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   15,
-        "tWTR":  2,
-        "tREFI": 7800,
-        "tRFC":  70
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
-            self.timing_settings)
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 2
+    tREFI = 7800
+    tRFC  = 70
 
 
 class MT41J128M16(SDRAMModule):
-    geom_settings = {
-        "nbanks": 8,
-        "nrows":  16384,
-        "ncols":  1024,
-    }
-    timing_settings = {
-        "tRP":   15,
-        "tRCD":  15,
-        "tWR":   15,
-        "tWTR":  3,
-        "tREFI": 64*1000*1000/16384,
-        "tRFC":  260,
-    }
-    def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
-            self.timing_settings)
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    tRP   = 15
+    tRCD  = 15
+    tWR   = 15
+    tWTR  = 3
+    tREFI = 64*1000*1000/16384
+    tRFC  = 260