O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).

The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 372e76b71c014c35f18704380aa6b2f57bbd464d..e9e3fea968e0651a4b7af67d7dedc1877bd5907a 100644 (file)
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -63,8 +63,6 @@ class DerivO3CPUParams;
  */
 template <class Impl>
 class LSQUnit {
-  protected:
-    typedef TheISA::IntReg IntReg;
   public:
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -338,7 +336,7 @@ class LSQUnit {
         /** The size of the store. */
         int size;
         /** The store data. */
-        char data[sizeof(IntReg)];
+        char data[16];
         /** Whether or not the store is split into two requests. */
         bool isSplit;
         /** Whether or not the store can writeback. */