[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Tue, 24 Mar 2020 10:50:57 +0000 (10:50 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Tue, 24 Mar 2020 10:50:59 +0000 (10:50 +0000)
f3/491ef3145ba317f3e51a962c6683e324a17900 [new file with mode: 0644]

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+Date: Tue, 24 Mar 2020 10:50:57 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
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+Subject: [libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or
+ partial) needed
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