ARM systems require local exclusive monitors for the implementation of
synchronization primitives between processors. A ruby memory system
needs to forward invalidations to the local exclusive monitors to
to correctly determine their state.
Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2904
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
# currently, 2 scenarios warrant forwarding evictions to the CPU:
# 1. The O3 model must keep the LSQ coherent with the caches
# 2. The x86 mwait instruction is built on top of coherence invalidations
- if options.cpu_type == "DerivO3CPU" or buildEnv['TARGET_ISA'] == 'x86':
+ # 3. The local exclusive monitor in ARM systems
+ if options.cpu_type == "DerivO3CPU" or \
+ buildEnv['TARGET_ISA'] in ('x86', 'arm'):
return True
return False