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lkcl
<lkcl@web>
Wed, 11 Mar 2020 04:40:51 +0000
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IkiWiki
<ikiwiki.info>
Wed, 11 Mar 2020 04:40:51 +0000
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3d_gpu/architecture/decoder.mdwn
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b/3d_gpu/architecture/decoder.mdwn
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3d_gpu/architecture/decoder.mdwn
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3d_gpu/architecture/decoder.mdwn
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The decoder is in charge of translating the RISCV or POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR that will switch which architecture it treats an instruction as.
+Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb=HEAD>
+
## POWER
### Fixed point instructions