SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are...

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index ffe0546fbed1ed21557d759a77cebd036cfd8924..fffd2da6cec03f30f4596eade1c562a735f147f9 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -85,9 +85,9 @@ class SoCCore(Module):
                 # CPU parameters
                 cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
                 # ROM parameters
-                integrated_rom_size=0x8000, integrated_rom_init=[],
+                integrated_rom_size=0, integrated_rom_init=[],
                 # SRAM parameters
-                integrated_sram_size=0x1000, integrated_sram_init=[],
+                integrated_sram_size=0, integrated_sram_init=[],
                 # MAIN_RAM parameters
                 integrated_main_ram_size=0, integrated_main_ram_init=[],
                 # CSR parameters
@@ -139,8 +139,10 @@ class SoCCore(Module):
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
-        self.integrated_sram_size       = integrated_sram_size
-        self.integrated_main_ram_size   = integrated_main_ram_size
+        if cpu_type is not None and integrated_sram_size == 0:
+            integrated_sram_size = 0x1000
+        self.integrated_sram_size     = integrated_sram_size
+        self.integrated_main_ram_size = integrated_main_ram_size
 
         assert csr_data_width in [8, 16, 32]
         self.csr_data_width    = csr_data_width