---------- Begin Simulation Statistics ----------
-sim_seconds 5.154240 # Number of seconds simulated
-sim_ticks 5154239928000 # Number of ticks simulated
-final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.122213 # Number of seconds simulated
+sim_ticks 5122212682000 # Number of ticks simulated
+final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 159835 # Simulator instruction rate (inst/s)
-host_op_rate 315937 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2019388964 # Simulator tick rate (ticks/s)
-host_mem_usage 759104 # Number of bytes of host memory used
-host_seconds 2552.38 # Real time elapsed on the host
-sim_insts 407959851 # Number of instructions simulated
-sim_ops 806389826 # Number of ops (including micro ops) simulated
+host_inst_rate 132606 # Simulator instruction rate (inst/s)
+host_op_rate 262116 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1665061517 # Simulator tick rate (ticks/s)
+host_mem_usage 804736 # Number of bytes of host memory used
+host_seconds 3076.29 # Real time elapsed on the host
+sim_insts 407934867 # Number of instructions simulated
+sim_ops 806343968 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 185029 # Number of read requests accepted
-system.physmem.writeReqs 196407 # Number of write requests accepted
-system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
-system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11576 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11057 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12153 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11198 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11802 # Per bank write bursts
-system.physmem.perBankRdBursts::5 11348 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11143 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11153 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11425 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11213 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11332 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11504 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11762 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12902 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11974 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11385 # Per bank write bursts
-system.physmem.perBankWrBursts::0 11439 # Per bank write bursts
-system.physmem.perBankWrBursts::1 10429 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10485 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9453 # Per bank write bursts
-system.physmem.perBankWrBursts::4 11713 # Per bank write bursts
-system.physmem.perBankWrBursts::5 11103 # Per bank write bursts
-system.physmem.perBankWrBursts::6 10277 # Per bank write bursts
-system.physmem.perBankWrBursts::7 10587 # Per bank write bursts
-system.physmem.perBankWrBursts::8 10639 # Per bank write bursts
-system.physmem.perBankWrBursts::9 10347 # Per bank write bursts
-system.physmem.perBankWrBursts::10 10880 # Per bank write bursts
-system.physmem.perBankWrBursts::11 10311 # Per bank write bursts
-system.physmem.perBankWrBursts::12 10712 # Per bank write bursts
-system.physmem.perBankWrBursts::13 11096 # Per bank write bursts
-system.physmem.perBankWrBursts::14 11110 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9917 # Per bank write bursts
+system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 185645 # Number of read requests accepted
+system.physmem.writeReqs 196237 # Number of write requests accepted
+system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
+system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11253 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10547 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11972 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11655 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11971 # Per bank write bursts
+system.physmem.perBankRdBursts::5 11254 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11364 # Per bank write bursts
+system.physmem.perBankRdBursts::7 11315 # Per bank write bursts
+system.physmem.perBankRdBursts::8 11445 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11672 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11062 # Per bank write bursts
+system.physmem.perBankRdBursts::11 11423 # Per bank write bursts
+system.physmem.perBankRdBursts::12 12308 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12737 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11748 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11789 # Per bank write bursts
+system.physmem.perBankWrBursts::0 11864 # Per bank write bursts
+system.physmem.perBankWrBursts::1 10686 # Per bank write bursts
+system.physmem.perBankWrBursts::2 10651 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9860 # Per bank write bursts
+system.physmem.perBankWrBursts::4 10294 # Per bank write bursts
+system.physmem.perBankWrBursts::5 10368 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9733 # Per bank write bursts
+system.physmem.perBankWrBursts::7 9712 # Per bank write bursts
+system.physmem.perBankWrBursts::8 9632 # Per bank write bursts
+system.physmem.perBankWrBursts::9 10471 # Per bank write bursts
+system.physmem.perBankWrBursts::10 10725 # Per bank write bursts
+system.physmem.perBankWrBursts::11 10392 # Per bank write bursts
+system.physmem.perBankWrBursts::12 11457 # Per bank write bursts
+system.physmem.perBankWrBursts::13 11384 # Per bank write bursts
+system.physmem.perBankWrBursts::14 11667 # Per bank write bursts
+system.physmem.perBankWrBursts::15 11109 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 48 # Number of times write queue was full causing retry
-system.physmem.totGap 5154239876000 # Total gap between requests
+system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
+system.physmem.totGap 5122212630000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 185029 # Read request sizes (log2)
+system.physmem.readPktSize::6 185645 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 196407 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 196237 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7339 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8415 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7894 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8094 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7725 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 10840 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8567 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7987 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1631 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1321 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 2521 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 2967 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 2476 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 2901 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 3411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 2551 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 2324 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 2194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 2613 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads
-system.physmem.totQLat 2002245948 # Total ticks spent queuing
-system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads
+system.physmem.totQLat 2015945224 # Total ticks spent queuing
+system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing
-system.physmem.readRowHits 151945 # Number of row buffer hits during reads
-system.physmem.writeRowHits 129899 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes
-system.physmem.avgGap 13512725.27 # Average gap between requests
-system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.747042 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states
-system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing
+system.physmem.readRowHits 152167 # Number of row buffer hits during reads
+system.physmem.writeRowHits 129451 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
+system.physmem.avgGap 13413076.89 # Average gap between requests
+system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.738637 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states
+system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.766215 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states
-system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states
+system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.766596 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states
+system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 86886659 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits
+system.cpu.branchPred.lookups 86818912 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 452015949 # number of cpu cycles simulated
+system.cpu.numCycles 449999443 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24276361 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued
-system.cpu.iq.rate 1.823454 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854954817 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 506 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued
+system.cpu.iq.rate 1.830580 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83301836 # Number of branches executed
-system.cpu.iew.exec_stores 9170146 # Number of stores executed
-system.cpu.iew.exec_rate 1.819883 # Inst execution rate
-system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640992347 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value
+system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83256358 # Number of branches executed
+system.cpu.iew.exec_stores 9110199 # Number of stores executed
+system.cpu.iew.exec_rate 1.826976 # Inst execution rate
+system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640695638 # num instructions producing a value
+system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407959851 # Number of instructions committed
-system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407934867 # Number of instructions committed
+system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22418298 # Number of memory references committed
-system.cpu.commit.loads 13992664 # Number of loads committed
-system.cpu.commit.membars 471797 # Number of memory barriers committed
-system.cpu.commit.branches 82198639 # Number of branches committed
+system.cpu.commit.refs 22410853 # Number of memory references committed
+system.cpu.commit.loads 13990304 # Number of loads committed
+system.cpu.commit.membars 471837 # Number of memory barriers committed
+system.cpu.commit.branches 82192569 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735203522 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155963 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction
+system.cpu.commit.int_insts 735158454 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155650 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
-system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
-system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407959851 # Number of Instructions Simulated
-system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads
-system.cpu.int_regfile_writes 656084038 # number of integer regfile writes
-system.cpu.fp_regfile_reads 176 # number of floating regfile reads
-system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads
-system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes
-system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads
-system.cpu.misc_regfile_writes 400328 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 1659836 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1268308634 # The number of ROB reads
+system.cpu.rob.rob_writes 1663603607 # The number of ROB writes
+system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407934867 # Number of Instructions Simulated
+system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads
+system.cpu.int_regfile_writes 655727641 # number of integer regfile writes
+system.cpu.fp_regfile_reads 182 # number of floating regfile reads
+system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads
+system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes
+system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads
+system.cpu.misc_regfile_writes 399949 # number of misc regfile writes
+system.cpu.dcache.tags.replacements 1659310 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits
-system.cpu.dcache.overall_hits::total 19127628 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses
-system.cpu.dcache.overall_misses::total 2548491 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits
+system.cpu.dcache.overall_hits::total 19059166 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses
+system.cpu.dcache.overall_misses::total 2547706 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks
-system.cpu.dcache.writebacks::total 1561658 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks
+system.cpu.dcache.writebacks::total 1560749 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 1000631 # number of replacements
-system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 996925 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits
-system.cpu.icache.overall_hits::total 8114183 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses
-system.cpu.icache.overall_misses::total 1066954 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits
+system.cpu.icache.overall_hits::total 8050243 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses
+system.cpu.icache.overall_misses::total 1066046 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 112684 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 112729 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.768450 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048248 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.172226 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989163 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 64030 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977020 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 35101682 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 35101682 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67331 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13137 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 984666 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1336353 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2401487 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1585305 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 154346 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 154346 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 67331 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 13137 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 984666 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1490699 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2555833 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 67331 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 13137 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 984666 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1490699 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2555833 # number of overall hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1489532 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16391 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 35623 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 52085 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1473 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1473 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133459 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133459 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 16363 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 35684 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 16391 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 169082 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 185544 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 169730 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 16391 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 169082 # number of overall misses
-system.cpu.l2cache.overall_misses::total 185544 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6193250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 446000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1375483774 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3059797000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 4441920024 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22673320 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 22673320 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10319199473 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 10319199473 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6193250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 446000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1375483774 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 13378996473 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 14761119497 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6193250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 446000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1375483774 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 13378996473 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 14761119497 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67397 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13142 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001057 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1371976 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2453572 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 287805 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 287805 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67397 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 13142 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1001057 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1659781 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2741377 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67397 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 13142 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1001057 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1659781 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2741377 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000979 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000380 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016374 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025965 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021228 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818788 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463713 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.463713 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000979 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000380 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016374 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.101870 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.067683 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000979 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000380 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016374 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.101870 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.067683 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89200 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776 # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses
+system.cpu.l2cache.overall_misses::total 186166 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 103019 # number of writebacks
-system.cpu.l2cache.writebacks::total 103019 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks
+system.cpu.l2cache.writebacks::total 102850 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16388 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35622 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 52081 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1473 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 1473 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133459 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133459 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 16388 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 169081 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 185540 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 16388 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 169081 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 185540 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5361750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 383000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1170197226 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2615090750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3791032726 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27003455 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27003455 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8650755527 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8650755527 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5361750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 383000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170197226 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11265846277 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 12441788253 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5361750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 383000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170197226 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11265846277 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 12441788253 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88987317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88987317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2410942500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2410942500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91398260000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91398260000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021227 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818788 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818788 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463713 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463713 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.067681 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.067681 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76600 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002294 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123530 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 59545 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 61672 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47688 1.09% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 223900 # Transaction distribution
-system.iobus.trans_dist::ReadResp 223900 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57738 # Transaction distribution
-system.iobus.trans_dist::WriteResp 11018 # Transaction distribution
+system.iobus.trans_dist::ReadReq 223899 # Transaction distribution
+system.iobus.trans_dist::ReadResp 223899 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
+system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1650 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1650 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47582 # number of replacements
-system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use
+system.iocache.tags.replacements 47572 # number of replacements
+system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428724 # Number of tag accesses
-system.iocache.tags.data_accesses 428724 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 916 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428643 # Number of tag accesses
+system.iocache.tags.data_accesses 428643 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses
-system.iocache.demand_misses::total 916 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses
-system.iocache.overall_misses::total 916 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
+system.iocache.demand_misses::total 907 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
+system.iocache.overall_misses::total 907 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 46668 # number of writebacks
-system.iocache.writebacks::total 46668 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 657690 # Transaction distribution
-system.membus.trans_dist::ReadResp 657682 # Transaction distribution
+system.membus.trans_dist::ReadReq 657725 # Transaction distribution
+system.membus.trans_dist::ReadResp 657721 # Transaction distribution
system.membus.trans_dist::WriteReq 13919 # Transaction distribution
system.membus.trans_dist::WriteResp 13919 # Transaction distribution
-system.membus.trans_dist::Writeback 149687 # Transaction distribution
+system.membus.trans_dist::Writeback 149517 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133182 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133180 # Transaction distribution
-system.membus.trans_dist::MessageReq 1650 # Transaction distribution
-system.membus.trans_dist::MessageResp 1650 # Transaction distribution
-system.membus.trans_dist::BadAddressError 8 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1640 # Total snoops (count)
-system.membus.snoop_fanout::samples 384867 # Request fanout histogram
+system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133760 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133758 # Transaction distribution
+system.membus.trans_dist::MessageReq 1643 # Transaction distribution
+system.membus.trans_dist::MessageResp 1643 # Transaction distribution
+system.membus.trans_dist::BadAddressError 4 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1635 # Total snoops (count)
+system.membus.snoop_fanout::samples 385314 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 384867 # Request fanout histogram
-system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 385314 # Request fanout histogram
+system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2211768878 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 51465743 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
---------- Begin Simulation Statistics ----------
-sim_seconds 5.134221 # Number of seconds simulated
-sim_ticks 5134220888000 # Number of ticks simulated
-final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.133731 # Number of seconds simulated
+sim_ticks 5133731116500 # Number of ticks simulated
+final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 243170 # Simulator instruction rate (inst/s)
-host_op_rate 483430 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5119785775 # Simulator tick rate (ticks/s)
-host_mem_usage 964244 # Number of bytes of host memory used
-host_seconds 1002.82 # Real time elapsed on the host
-sim_insts 243855553 # Number of instructions simulated
-sim_ops 484792888 # Number of ops (including micro ops) simulated
+host_inst_rate 201130 # Simulator instruction rate (inst/s)
+host_op_rate 399856 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4230291451 # Simulator tick rate (ticks/s)
+host_mem_usage 1019904 # Number of bytes of host memory used
+host_seconds 1213.56 # Real time elapsed on the host
+sim_insts 244084329 # Number of instructions simulated
+sim_ops 485251122 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 442496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5387840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 144896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1908224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 377856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 3143424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 445760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5319424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 180800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1995776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 334336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 3134080 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11436096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 442496 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 144896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 377856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 965248 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9176704 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9176704 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11441152 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 445760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 180800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 334336 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 960896 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9198080 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9198080 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6914 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 84185 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2264 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 29816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5904 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 49116 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 83116 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2825 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 31184 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5224 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 48970 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 178689 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 143386 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143386 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 178768 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 143720 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 143720 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 86186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1049398 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 28222 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 371668 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 524 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 73596 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 612249 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2227426 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 86186 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 28222 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 73596 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 188003 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1787361 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1787361 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1787361 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 86830 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1036171 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35218 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 388757 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 65125 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 610488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2228623 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 86830 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35218 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 65125 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 187173 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1791695 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1791695 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1791695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 86186 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1049398 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 28222 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 371668 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 73596 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 612249 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4014786 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 87585 # Number of read requests accepted
-system.physmem.writeReqs 96690 # Number of write requests accepted
-system.physmem.readBursts 87585 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 96690 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5601728 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5458112 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5605440 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6188160 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 11390 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 914 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 5700 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5150 # Per bank write bursts
-system.physmem.perBankRdBursts::2 4887 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5253 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5094 # Per bank write bursts
-system.physmem.perBankRdBursts::5 4483 # Per bank write bursts
-system.physmem.perBankRdBursts::6 5146 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4650 # Per bank write bursts
-system.physmem.perBankRdBursts::8 5914 # Per bank write bursts
-system.physmem.perBankRdBursts::9 5792 # Per bank write bursts
-system.physmem.perBankRdBursts::10 5352 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5127 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5714 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6636 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6391 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6238 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5924 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5309 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4960 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5064 # Per bank write bursts
-system.physmem.perBankWrBursts::4 5666 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4857 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5361 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4594 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5275 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5755 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5195 # Per bank write bursts
-system.physmem.perBankWrBursts::11 4824 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5173 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6061 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5642 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5623 # Per bank write bursts
+system.physmem.bw_total::cpu0.inst 86830 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1036171 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35218 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 388757 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 65125 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 610488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4020318 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 88682 # Number of read requests accepted
+system.physmem.writeReqs 112966 # Number of write requests accepted
+system.physmem.readBursts 88682 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 112966 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5672000 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 3648 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6262656 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5675648 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7229824 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 57 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 15112 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 1053 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 5542 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5155 # Per bank write bursts
+system.physmem.perBankRdBursts::2 5253 # Per bank write bursts
+system.physmem.perBankRdBursts::3 5290 # Per bank write bursts
+system.physmem.perBankRdBursts::4 5356 # Per bank write bursts
+system.physmem.perBankRdBursts::5 4920 # Per bank write bursts
+system.physmem.perBankRdBursts::6 5387 # Per bank write bursts
+system.physmem.perBankRdBursts::7 5003 # Per bank write bursts
+system.physmem.perBankRdBursts::8 5335 # Per bank write bursts
+system.physmem.perBankRdBursts::9 5304 # Per bank write bursts
+system.physmem.perBankRdBursts::10 5486 # Per bank write bursts
+system.physmem.perBankRdBursts::11 5354 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5802 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6837 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6164 # Per bank write bursts
+system.physmem.perBankRdBursts::15 6437 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6158 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6179 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6254 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6080 # Per bank write bursts
+system.physmem.perBankWrBursts::4 5432 # Per bank write bursts
+system.physmem.perBankWrBursts::5 5660 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6180 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5898 # Per bank write bursts
+system.physmem.perBankWrBursts::8 5226 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5788 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6663 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6618 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6477 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6666 # Per bank write bursts
+system.physmem.perBankWrBursts::14 5929 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6646 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 29 # Number of times write queue was full causing retry
-system.physmem.totGap 5133220754000 # Total gap between requests
+system.physmem.numWrRetry 21 # Number of times write queue was full causing retry
+system.physmem.totGap 5132592336000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 87585 # Read request sizes (log2)
+system.physmem.readPktSize::6 88682 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 96690 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 81722 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4619 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 680 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 175 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 112966 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 81919 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 5154 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1007 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 209 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1039 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3310 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3809 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3692 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 3794 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4270 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 3935 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4892 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 3751 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4127 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4040 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 759 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 534 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 685 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1249 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1191 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1037 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1374 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1067 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1059 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1078 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 775 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 568 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 373 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 186 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 118 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38708 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 285.721608 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 170.408148 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 310.834116 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 15365 39.69% 39.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 9282 23.98% 63.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4036 10.43% 74.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2303 5.95% 80.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1514 3.91% 83.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1118 2.89% 86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 653 1.69% 88.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 582 1.50% 90.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3855 9.96% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38708 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3628 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.124587 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 196.006736 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 3625 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1363 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3421 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3754 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4037 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3921 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4080 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4330 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4535 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4412 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5377 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5007 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4290 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6323 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4956 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4558 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4427 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1157 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 749 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1599 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1755 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1610 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1912 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1553 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1348 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1351 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1565 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 1119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 976 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 485 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 40590 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 294.012121 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 173.528709 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 319.654231 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15917 39.21% 39.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9832 24.22% 63.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4000 9.85% 73.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2295 5.65% 78.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1624 4.00% 82.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1126 2.77% 85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 717 1.77% 87.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 617 1.52% 89.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4462 10.99% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 40590 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3784 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.420983 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 192.521538 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 3781 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3628 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3628 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 23.506891 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.576033 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 38.070070 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15 79 2.18% 2.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 3330 91.79% 93.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 63 1.74% 95.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 14 0.39% 96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 6 0.17% 96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 13 0.36% 96.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 6 0.17% 96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 13 0.36% 97.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 16 0.44% 97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 18 0.50% 98.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 3 0.08% 98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 8 0.22% 98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 33 0.91% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 3 0.08% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 1 0.03% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.06% 99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 2 0.06% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 3 0.08% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 1 0.03% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 7 0.19% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 3 0.08% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 1 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 2 0.06% 99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 3784 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3784 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 25.859937 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.216089 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 44.163335 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-15 82 2.17% 2.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 3425 90.51% 92.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 68 1.80% 94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 12 0.32% 94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 7 0.18% 94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 15 0.40% 95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 10 0.26% 95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 22 0.58% 96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 22 0.58% 96.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 17 0.45% 97.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 6 0.16% 97.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 22 0.58% 97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 36 0.95% 98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 7 0.18% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 2 0.05% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 3 0.08% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 1 0.03% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 1 0.03% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 5 0.13% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 4 0.11% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 6 0.16% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 5 0.13% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.03% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 1 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 1 0.03% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3628 # Writes before turning the bus around for reads
-system.physmem.totQLat 973946232 # Total ticks spent queuing
-system.physmem.totMemAccLat 2615077482 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 437635000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11127.38 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 3784 # Writes before turning the bus around for reads
+system.physmem.totQLat 1019929900 # Total ticks spent queuing
+system.physmem.totMemAccLat 2681648650 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 443125000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11508.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29877.38 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.09 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30258.38 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.41 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 10.98 # Average write queue length when enqueuing
-system.physmem.readRowHits 70024 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64077 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.00 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes
-system.physmem.avgGap 27856305.81 # Average gap between requests
-system.physmem.pageHitRate 77.59 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 138605040 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 75351375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 314831400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 270442800 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 94326783165 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2239415376750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 2584559149170 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.799253 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 3683386249962 # Time in different power states
-system.physmem_0.memoryStateTime::REF 127820940000 # Time in different power states
+system.physmem.avgWrQLen 11.85 # Average write queue length when enqueuing
+system.physmem.readRowHits 70792 # Number of row buffer hits during reads
+system.physmem.writeRowHits 75088 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 76.73 # Row buffer hit rate for writes
+system.physmem.avgGap 25453227.09 # Average gap between requests
+system.physmem.pageHitRate 78.23 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 147351960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 80169375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 326866800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 309938400 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 94629197520 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2236697889750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 2582234091885 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.903813 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 3683333970938 # Time in different power states
+system.physmem_0.memoryStateTime::REF 127833680000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 17097201288 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 17533181312 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 154027440 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 83877750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 367863600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 282191040 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 95207179230 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2235926942250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 2582039839950 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.929569 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 3682087997664 # Time in different power states
-system.physmem_1.memoryStateTime::REF 127820940000 # Time in different power states
+system.physmem_1.actEnergy 159410160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 86781750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 364408200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 323974080 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 95188577850 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2235010334250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 2581176164370 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.974824 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 3682508953468 # Time in different power states
+system.physmem_1.memoryStateTime::REF 127833680000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 18395204336 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 18355082532 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 861071319 # number of cpu cycles simulated
+system.cpu0.numCycles 819384850 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 71289400 # Number of instructions committed
-system.cpu0.committedOps 145467698 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 133359316 # Number of integer alu accesses
+system.cpu0.committedInsts 70809878 # Number of instructions committed
+system.cpu0.committedOps 144569383 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 132504639 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 922812 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14140303 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 133359316 # number of integer instructions
+system.cpu0.num_func_calls 914830 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14060186 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 132504639 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 244470794 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 114705006 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 242769596 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 113987635 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 82965986 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 55469495 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13497529 # number of memory refs
-system.cpu0.num_load_insts 10019587 # Number of load instructions
-system.cpu0.num_store_insts 3477942 # Number of store instructions
-system.cpu0.num_idle_cycles 817633663.650796 # Number of idle cycles
-system.cpu0.num_busy_cycles 43437655.349204 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.050446 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.949554 # Percentage of idle cycles
-system.cpu0.Branches 15408320 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 89223 0.06% 0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu 131776877 90.59% 90.65% # Class of executed instruction
-system.cpu0.op_class::IntMult 58105 0.04% 90.69% # Class of executed instruction
-system.cpu0.op_class::IntDiv 48148 0.03% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.72% # Class of executed instruction
-system.cpu0.op_class::MemRead 10017918 6.89% 97.61% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3477942 2.39% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 82531896 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 55153606 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13358556 # number of memory refs
+system.cpu0.num_load_insts 9930193 # Number of load instructions
+system.cpu0.num_store_insts 3428363 # Number of store instructions
+system.cpu0.num_idle_cycles 778171794.138464 # Number of idle cycles
+system.cpu0.num_busy_cycles 41213055.861536 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.050298 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.949702 # Percentage of idle cycles
+system.cpu0.Branches 15315720 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 88912 0.06% 0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu 131019698 90.63% 90.69% # Class of executed instruction
+system.cpu0.op_class::IntMult 57722 0.04% 90.73% # Class of executed instruction
+system.cpu0.op_class::IntDiv 46561 0.03% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.76% # Class of executed instruction
+system.cpu0.op_class::MemRead 9928558 6.87% 97.63% # Class of executed instruction
+system.cpu0.op_class::MemWrite 3428363 2.37% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 145468213 # Class of executed instruction
+system.cpu0.op_class::total 144569814 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 1637783 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999406 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19710876 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1638295 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 12.031335 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1636339 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999246 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 19643358 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1636851 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 12.000700 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.289579 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 344.626695 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.083132 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.281816 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.673099 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.045084 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.510577 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.541861 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.946808 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454122 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499105 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.046771 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88682212 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88682212 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4830179 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 2466757 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4264396 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 11561332 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3346491 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1735459 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 3006073 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 8088023 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19837 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10092 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29821 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 59750 # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8176670 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 4202216 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 7270469 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 19649355 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8196507 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 4212308 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 7300290 # number of overall hits
-system.cpu0.dcache.overall_hits::total 19709105 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 348359 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 159608 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 811619 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1319586 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 127641 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 64125 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 133967 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 325733 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145510 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 64697 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196344 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 406551 # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 476000 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 223733 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 945586 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1645319 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 621510 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 288430 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1141930 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2051870 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193925000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11673600356 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 13867525356 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2608735779 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4432412697 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7041148476 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 4802660779 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 16106013053 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 20908673832 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 4802660779 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 16106013053 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 20908673832 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 5178538 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 2626365 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 5076015 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 12880918 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 3474132 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1799584 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 3140040 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 8413756 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165347 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74789 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226165 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 466301 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 8652670 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 4425949 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 8216055 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 21294674 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 8818017 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 4500738 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 8442220 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 21760975 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067270 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060771 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159893 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.102445 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036740 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035633 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042664 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.038714 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.880028 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865060 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868145 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871864 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055012 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050550 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115090 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.077264 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070482 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064085 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135264 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.094291 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13745.708235 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14383.103841 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10508.997031 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40682.039439 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 33085.854703 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21616.319120 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21466.036655 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17032.837894 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 12707.975676 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16651.044548 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14104.203456 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10190.057768 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 161116 # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses 88441515 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 88441515 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4745925 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 2412981 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 4334563 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 11493469 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3299103 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1688891 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 3099986 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 8087980 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19676 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9874 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30514 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 60064 # number of SoftPFReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 8045028 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 4101872 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 7434549 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 19581449 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 8064704 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 4111746 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 7465063 # number of overall hits
+system.cpu0.dcache.overall_hits::total 19641513 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 345343 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 160729 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 822143 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1328215 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 125592 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 64251 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 135437 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 325280 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145872 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63796 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196481 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 406149 # number of SoftPFReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 470935 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 224980 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 957580 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1653495 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 616807 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 288776 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1154061 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2059644 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2230470250 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12318599402 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 14549069652 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2662717793 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4381161307 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7043879100 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 4893188043 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 16699760709 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 21592948752 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 4893188043 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 16699760709 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 21592948752 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 5091268 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 2573710 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 5156706 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 12821684 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 3424695 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1753142 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 3235423 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 8413260 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165548 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73670 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226995 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 466213 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 8515963 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 4326852 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 8392129 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 21234944 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 8681511 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 4400522 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 8619124 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 21701157 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067830 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.062450 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159432 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.103591 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036672 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036649 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041861 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.038663 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.881146 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865970 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.865574 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871166 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055300 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051996 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114105 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.077867 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071048 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065623 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133895 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.094909 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13877.211020 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14983.524037 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10953.851336 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41442.433472 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32348.333963 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21654.817696 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21749.435697 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17439.546261 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13058.974325 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16944.580031 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14470.431553 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10483.825725 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 172709 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 19020 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 19385 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.470873 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.909414 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 1546722 # number of writebacks
-system.cpu0.dcache.writebacks::total 1546722 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 374785 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 374834 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1569 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32139 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 33708 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 1618 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 406924 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 408542 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 1618 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 406924 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 408542 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159559 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 436834 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 596393 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62556 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 101828 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 164384 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64697 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 192960 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 257657 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 222115 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 538662 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 760777 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 286812 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 731622 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1018434 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1953809500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5644023259 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7597832759 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2418621221 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3692192265 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6110813486 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904952750 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2733042751 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3637995501 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4372430721 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9336215524 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 13708646245 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5277383471 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12069258275 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 17346641746 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30408890000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33050179000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63459069000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531811000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 800665000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1332476000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30940701000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33850844000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64791545000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060753 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086058 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046301 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034761 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032429 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019538 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865060 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.853182 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.552555 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050185 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065562 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.035726 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063726 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086662 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.046801 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.059821 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12920.292969 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12739.641074 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38663.297222 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36259.106189 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37174.016242 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13987.553519 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14163.778768 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.529068 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19685.436468 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17332.233430 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18019.270095 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18400.148777 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16496.576477 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17032.661661 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 1546428 # number of writebacks
+system.cpu0.dcache.writebacks::total 1546428 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 54 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 384012 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 384066 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1567 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32068 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 33635 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1621 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 416080 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 417701 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1621 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 416080 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 417701 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 160675 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438131 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 598806 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62684 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103369 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 166053 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63795 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193085 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 256880 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 223359 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 541500 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 764859 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2470174689 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3635352900 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6105527589 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 932249000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770809752 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3703058752 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4458692939 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9348693664 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13807386603 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5390941939 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12119503416 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 17510445355 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30496812500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33031149000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63527961500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600115500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 761942500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1362058000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31096928000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33793091500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64890019500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.062429 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084963 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046703 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035755 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031949 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019737 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865956 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850613 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.550993 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.051622 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064525 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.036019 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065255 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085227 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.047082 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.027696 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13040.256827 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12862.027124 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39406.781459 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35168.695644 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36768.547325 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14613.198527 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14350.207173 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14415.519900 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19962.002601 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17264.438899 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 877463 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.822061 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 128690361 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 877975 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 146.576339 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 150549344000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.387940 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 146.288168 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 89.145952 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.537867 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.285719 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.174113 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997699 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 871419 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 127964014 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 871931 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 146.759335 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 150504235000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.667168 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.237667 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.336510 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509116 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.279761 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.207688 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.996565 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 130472306 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 130472306 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 86685680 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 38800184 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3204497 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 128690361 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 86685680 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 38800184 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3204497 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 128690361 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 86685680 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 38800184 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3204497 # number of overall hits
-system.cpu0.icache.overall_hits::total 128690361 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 302042 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 162655 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 439255 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 903952 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 302042 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 162655 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 439255 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 903952 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 302042 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 162655 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 439255 # number of overall misses
-system.cpu0.icache.overall_misses::total 903952 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2276697249 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6082026148 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 8358723397 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 2276697249 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 6082026148 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 8358723397 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 2276697249 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 6082026148 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 8358723397 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 86987722 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 38962839 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 3643752 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 129594313 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 86987722 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 38962839 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 3643752 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 129594313 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 86987722 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 38962839 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 3643752 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 129594313 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003472 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004175 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120550 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.006975 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003472 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004175 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120550 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.006975 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003472 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004175 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120550 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.006975 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13997.093535 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13846.230886 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 9246.866423 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 9246.866423 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 9246.866423 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 5936 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 289 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.539792 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses 129734477 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 129734477 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 86118928 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 38597787 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 3247299 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 127964014 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 86118928 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 38597787 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 3247299 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 127964014 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 86118928 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 38597787 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 3247299 # number of overall hits
+system.cpu0.icache.overall_hits::total 127964014 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 294029 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 171033 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 433450 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 898512 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 294029 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 171033 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 433450 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 898512 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 294029 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 171033 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 433450 # number of overall misses
+system.cpu0.icache.overall_misses::total 898512 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424026997 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943573307 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 8367600304 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 2424026997 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 5943573307 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 8367600304 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 2424026997 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 5943573307 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 8367600304 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 86412957 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 38768820 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 3680749 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 128862526 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 86412957 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 38768820 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 3680749 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 128862526 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 86412957 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 38768820 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 3680749 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 128862526 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003403 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004412 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117761 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.006973 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003403 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004412 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117761 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.006973 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003403 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004412 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117761 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.006973 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14172.861360 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.246642 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.730719 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 9312.730719 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 9312.730719 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 7161 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 313 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.878594 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25959 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 25959 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 25959 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 25959 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 25959 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 25959 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162655 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 413296 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 575951 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 162655 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 413296 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 575951 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 162655 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 413296 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 575951 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2031893251 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5207377551 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 7239270802 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2031893251 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5207377551 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 7239270802 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2031893251 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5207377551 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 7239270802 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004444 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.004444 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.004444 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12569.247735 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 26561 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 26561 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 26561 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 26561 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 26561 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 26561 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 171033 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 406889 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 577922 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 171033 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 406889 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 577922 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 171033 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 406889 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 577922 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2166425503 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5084799831 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 7251225334 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2166425503 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5084799831 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 7251225334 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2166425503 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5084799831 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 7251225334 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004485 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.004485 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.004485 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12547.065753 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2606018109 # number of cpu cycles simulated
+system.cpu1.numCycles 2604016269 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 35373738 # Number of instructions committed
-system.cpu1.committedOps 68746890 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 63819737 # Number of integer alu accesses
+system.cpu1.committedInsts 35221864 # Number of instructions committed
+system.cpu1.committedOps 68477973 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 63543554 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 481772 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6496386 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 63819737 # number of integer instructions
+system.cpu1.num_func_calls 474559 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6488284 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 63543554 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 118130559 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 54973369 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 117503426 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 54764358 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36098608 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 26881383 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4684980 # number of memory refs
-system.cpu1.num_load_insts 2884758 # Number of load instructions
-system.cpu1.num_store_insts 1800222 # Number of store instructions
-system.cpu1.num_idle_cycles 2483538175.555252 # Number of idle cycles
-system.cpu1.num_busy_cycles 122479933.444748 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.046999 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.953001 # Percentage of idle cycles
-system.cpu1.Branches 7152522 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 34380 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 63978277 93.06% 93.11% # Class of executed instruction
-system.cpu1.op_class::IntMult 29063 0.04% 93.16% # Class of executed instruction
-system.cpu1.op_class::IntDiv 22112 0.03% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.19% # Class of executed instruction
-system.cpu1.op_class::MemRead 2883100 4.19% 97.38% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1800222 2.62% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 35994299 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 26824776 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4585615 # number of memory refs
+system.cpu1.num_load_insts 2831531 # Number of load instructions
+system.cpu1.num_store_insts 1754084 # Number of store instructions
+system.cpu1.num_idle_cycles 2478252415.347472 # Number of idle cycles
+system.cpu1.num_busy_cycles 125763853.652528 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.048296 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.951704 # Percentage of idle cycles
+system.cpu1.Branches 7131846 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 33642 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 63809884 93.18% 93.23% # Class of executed instruction
+system.cpu1.op_class::IntMult 28068 0.04% 93.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv 22761 0.03% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.31% # Class of executed instruction
+system.cpu1.op_class::MemRead 2829816 4.13% 97.44% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1754084 2.56% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 68747154 # Class of executed instruction
+system.cpu1.op_class::total 68478255 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 29503892 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 29503892 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 342810 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26694805 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 25976378 # Number of BTB hits
+system.cpu2.branchPred.lookups 29642945 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29642945 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 342109 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26793966 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 26087449 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.308739 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 611666 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 68809 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 155682865 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.363149 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 617263 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 68240 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 154815215 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 11322292 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 145393707 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 29503892 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26588044 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 142785185 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 717310 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 102884 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 9783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 8624 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 60469 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 854 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3643758 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 177822 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 3817 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 154648109 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.849994 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.031354 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 11226493 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 146138571 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29642945 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26704712 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 142088964 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 715876 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 100355 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 5095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 9800 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 59006 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 1044 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3680756 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 177933 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3589 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 153848066 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.868751 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.040918 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 98977108 64.00% 64.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 881864 0.57% 64.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23689941 15.32% 79.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 607646 0.39% 80.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 853753 0.55% 80.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 859687 0.56% 81.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 584791 0.38% 81.77% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 755278 0.49% 82.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27438041 17.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 97905187 63.64% 63.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 902052 0.59% 64.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23780045 15.46% 79.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 607949 0.40% 80.08% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 861058 0.56% 80.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 871308 0.57% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 586027 0.38% 81.58% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 774714 0.50% 82.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27559726 17.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 154648109 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.189513 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.933910 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10277895 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 94004330 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 21519674 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 4891128 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 359306 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 283040141 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 359306 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12341484 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 77022094 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4867618 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 24062417 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 12399480 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 281740718 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 206678 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 5855345 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 68061 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 4394741 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 336544944 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 615400877 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 377780143 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 207 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 323636169 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12908773 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 167322 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 168903 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 23920372 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6854331 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3831116 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 436605 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 369940 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 279698877 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 9552955 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.794181 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.395462 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 153848066 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.191473 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.943955 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10308577 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 93114688 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 23867360 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5032797 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 358589 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 284536277 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 358589 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 12446525 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 76456474 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4505534 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 26483485 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 12431465 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 283232358 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 203213 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 5874103 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 62488 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 4343022 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 338256341 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 618855518 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 379959971 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 144 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 325490778 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12765563 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 164991 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 166448 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 24511654 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6973831 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3905800 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 411343 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 337090 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 281177337 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 428187 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 278961410 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 111637 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 9401758 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 14188384 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 65116 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 153848066 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.813227 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.402216 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 91599661 59.23% 59.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5400101 3.49% 62.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3869243 2.50% 65.22% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 3752650 2.43% 67.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 22658386 14.65% 82.30% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 2693281 1.74% 84.04% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 23975807 15.50% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 476523 0.31% 99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 222457 0.14% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 90533816 58.85% 58.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5362080 3.49% 62.33% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3874219 2.52% 64.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 3850508 2.50% 67.35% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 22615321 14.70% 82.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 2805299 1.82% 83.88% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 24069627 15.65% 99.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 503741 0.33% 99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 233455 0.15% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 154648109 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 153848066 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 1665704 85.56% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.56% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 217161 11.15% 96.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 64057 3.29% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 1762451 85.95% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.95% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 222010 10.83% 96.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 66103 3.22% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 83075 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 266581381 96.08% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 59040 0.02% 96.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 53621 0.02% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 87 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 7156038 2.58% 98.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3533403 1.27% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 83756 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 267874850 96.03% 96.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 60171 0.02% 96.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 55540 0.02% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 52 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 7279557 2.61% 98.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3607484 1.29% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 277466645 # Type of FU issued
-system.cpu2.iq.rate 1.782256 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 289688673 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 244 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 727263 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 278961410 # Type of FU issued
+system.cpu2.iq.rate 1.801899 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 2050564 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 713932890 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 291011736 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 277302749 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 156 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 280928122 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 96 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 764231 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1301667 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 5946 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5330 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 686178 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1280710 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6256 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 5226 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 665708 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 750303 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 28695 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 750625 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 30616 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 359306 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 71000950 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 2910946 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 280131260 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 44826 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6854348 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3831116 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 254274 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 173954 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2389293 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5330 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 193600 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 205490 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 399090 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 276846611 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 7005762 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 563321 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 358589 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 70562607 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 2840752 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 281605524 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 45396 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6973831 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3905800 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 251212 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 165628 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2346507 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 5226 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 195667 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 202777 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 398444 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 278332986 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 7126227 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 571848 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 10447548 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 28131020 # Number of branches executed
-system.cpu2.iew.exec_stores 3441786 # Number of stores executed
-system.cpu2.iew.exec_rate 1.778273 # Inst execution rate
-system.cpu2.iew.wb_sent 276647008 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 275821721 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 215019240 # num instructions producing a value
-system.cpu2.iew.wb_consumers 352722264 # num instructions consuming a value
+system.cpu2.iew.exec_refs 10641796 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 28281444 # Number of branches executed
+system.cpu2.iew.exec_stores 3515569 # Number of stores executed
+system.cpu2.iew.exec_rate 1.797840 # Inst execution rate
+system.cpu2.iew.wb_sent 278129863 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 277302825 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 216123267 # num instructions producing a value
+system.cpu2.iew.wb_consumers 354504830 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.771690 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609599 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.791186 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609648 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 9550045 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 363403 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 345846 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 153217834 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.765971 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.651639 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 9397385 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 363071 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 345314 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 152442881 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.785612 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.660258 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 95448328 62.30% 62.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4376826 2.86% 65.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1280143 0.84% 65.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24626260 16.07% 82.06% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 968124 0.63% 82.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 723433 0.47% 83.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 420249 0.27% 83.44% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23244515 15.17% 98.61% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2129956 1.39% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 94319401 61.87% 61.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4425348 2.90% 64.77% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1302226 0.85% 65.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24740165 16.23% 81.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 979797 0.64% 82.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 733746 0.48% 82.98% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 423992 0.28% 83.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23324047 15.30% 98.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2194159 1.44% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 153217834 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 137192415 # Number of instructions committed
-system.cpu2.commit.committedOps 270578300 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 152442881 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 138052587 # Number of instructions committed
+system.cpu2.commit.committedOps 272203766 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8697618 # Number of memory references committed
-system.cpu2.commit.loads 5552680 # Number of loads committed
-system.cpu2.commit.membars 162630 # Number of memory barriers committed
-system.cpu2.commit.branches 27696347 # Number of branches committed
+system.cpu2.commit.refs 8933213 # Number of memory references committed
+system.cpu2.commit.loads 5693121 # Number of loads committed
+system.cpu2.commit.membars 162094 # Number of memory barriers committed
+system.cpu2.commit.branches 27859693 # Number of branches committed
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 247309305 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 454335 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 48751 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 261723532 96.73% 96.75% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 56607 0.02% 96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 51834 0.02% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5552622 2.05% 98.84% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3144938 1.16% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 248852946 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 461863 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 49962 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 263110099 96.66% 96.68% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 57933 0.02% 96.70% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 52599 0.02% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5693065 2.09% 98.81% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 3240092 1.19% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 431186663 # The number of ROB reads
-system.cpu2.rob.rob_writes 561693850 # The number of ROB writes
-system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1034756 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4900728082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 137192415 # Number of Instructions Simulated
-system.cpu2.committedOps 270578300 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.134777 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.134777 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.881230 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.881230 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 368834984 # number of integer regfile reads
-system.cpu2.int_regfile_writes 221067360 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 73020 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 140711927 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 108060819 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 90227595 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 143035 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 3553360 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3553360 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57725 # Transaction distribution
-system.iobus.trans_dist::WriteResp 11005 # Transaction distribution
+system.cpu2.commit.op_class_0::total 272203766 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 2194159 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 431819572 # The number of ROB reads
+system.cpu2.rob.rob_writes 564614589 # The number of ROB writes
+system.cpu2.timesIdled 120593 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 967149 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4904349916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 138052587 # Number of Instructions Simulated
+system.cpu2.committedOps 272203766 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.121422 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.121422 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.891725 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.891725 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 371027158 # number of integer regfile reads
+system.cpu2.int_regfile_writes 222252306 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 72988 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 141449053 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 108603776 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 90794642 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 144161 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 3553347 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3553347 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57679 # Transaction distribution
+system.iobus.trans_dist::WriteResp 10959 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1679 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1679 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1698 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1698 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082618 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082616 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7126912 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3358 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3358 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7225528 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 7126806 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3396 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3396 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7225448 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541309 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3569655 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6716 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6716 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6604187 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2698688 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 3569512 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6792 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6792 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 6604072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 2741680 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 21000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 5333000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 6074000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 16000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 141310000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 141309000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 414000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 285000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 78000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10425000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 10492000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 116029251 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 155889253 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 300958000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 301765000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 24266250 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 31644993 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1136000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1151000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47574 # number of replacements
-system.iocache.tags.tagsinuse 0.081409 # Cycle average of tags in use
+system.iocache.tags.replacements 47568 # number of replacements
+system.iocache.tags.tagsinuse 0.079964 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5000597695009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081409 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005088 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005088 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5000587823009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079964 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004998 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428661 # Number of tag accesses
-system.iocache.tags.data_accesses 428661 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428607 # Number of tag accesses
+system.iocache.tags.data_accesses 428607 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
-system.iocache.demand_misses::total 909 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
-system.iocache.overall_misses::total 909 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 125652013 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 125652013 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 3845868988 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 3845868988 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 125652013 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 125652013 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 125652013 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 125652013 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses
+system.iocache.demand_misses::total 903 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses
+system.iocache.overall_misses::total 903 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128377230 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 128377230 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 5164742030 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 5164742030 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 128377230 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 128377230 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 128377230 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 128377230 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 138231.037404 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 82317.401284 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 82317.401284 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 138231.037404 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 138231.037404 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 13512 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 142167.475083 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 110546.704409 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 110546.704409 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 142167.475083 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 142167.475083 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 17612 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 2030 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 2632 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.656158 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.691489 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 745 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 745 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21024 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 21024 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 745 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 745 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 745 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 745 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 86664503 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2752610998 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2752610998 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 86664503 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 86664503 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.819582 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.450000 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.450000 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.819582 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.819582 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 116328.191946 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130927.083238 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130927.083238 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 801 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28264 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 28264 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 801 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 801 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 801 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 86423212 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 3695010034 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3695010034 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 86423212 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 86423212 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.887043 # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.604966 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.604966 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.887043 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.887043 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 107894.147316 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130732.027809 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130732.027809 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 105420 # number of replacements
-system.l2c.tags.tagsinuse 64829.150073 # Cycle average of tags in use
-system.l2c.tags.total_refs 3714265 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 169452 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.919275 # Average number of references to valid blocks.
+system.l2c.tags.replacements 105369 # number of replacements
+system.l2c.tags.tagsinuse 64830.626845 # Cycle average of tags in use
+system.l2c.tags.total_refs 3705679 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 169446 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.869380 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 51423.363344 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134649 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1822.192254 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5065.443853 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 236.253380 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1546.126379 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.729356 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 913.877634 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 3810.029226 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.784658 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 50858.096780 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134526 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 1601.427587 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 5289.246768 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000914 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 232.896636 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 1549.888722 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.632040 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1227.720144 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 4063.582728 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.776033 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.027804 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.077293 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.003605 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.023592 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.013945 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.058136 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.989214 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64032 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 535 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3173 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 53036 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.977051 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 34034094 # Number of tag accesses
-system.l2c.tags.data_accesses 34034094 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 19379 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 10642 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 295114 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 477769 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 12495 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 7386 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 160391 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 220397 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 66650 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 14282 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 407368 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 616656 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2308529 # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst 0.024436 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.080708 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.003554 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.023649 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000116 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.018734 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.062005 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.989237 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 64077 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 4057 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 8155 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 51563 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.977737 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 33969935 # Number of tag accesses
+system.l2c.tags.data_accesses 33969935 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 19552 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 10769 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 287050 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 476755 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 13141 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 7558 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 168208 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 219838 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 66288 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 13297 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 401625 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 617193 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2301274 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks 1546722 # number of Writeback hits
-system.l2c.Writeback_hits::total 1546722 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 113 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 258 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 58538 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 36097 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 64817 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 159452 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 19379 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 10644 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 295114 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 536307 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 12495 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 7386 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 160391 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 256494 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 66650 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 14282 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 407368 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 681473 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2467983 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 19379 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 10644 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 295114 # number of overall hits
-system.l2c.overall_hits::cpu0.data 536307 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 12495 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 7386 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 160391 # number of overall hits
-system.l2c.overall_hits::cpu1.data 256494 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 66650 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 14282 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 407368 # number of overall hits
-system.l2c.overall_hits::cpu2.data 681473 # number of overall hits
-system.l2c.overall_hits::total 2467983 # number of overall hits
+system.l2c.Writeback_hits::writebacks 1546428 # number of Writeback hits
+system.l2c.Writeback_hits::total 1546428 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 105 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 96 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 248 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 55987 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 35553 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 67356 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 158896 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 19552 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 10771 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 287050 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 532742 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 13141 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 7558 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 168208 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 255391 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 66288 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 13297 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 401625 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 684549 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2460172 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 19552 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 10771 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 287050 # number of overall hits
+system.l2c.overall_hits::cpu0.data 532742 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 13141 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 7558 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 168208 # number of overall hits
+system.l2c.overall_hits::cpu1.data 255391 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 66288 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 13297 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 401625 # number of overall hits
+system.l2c.overall_hits::cpu2.data 684549 # number of overall hits
+system.l2c.overall_hits::total 2460172 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6915 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 16100 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 2264 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 3859 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 5904 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 13093 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 48182 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 632 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 257 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 496 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 68358 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 26158 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 36472 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 130988 # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6966 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 14460 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 2825 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4632 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 5226 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 13983 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 48133 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 556 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 254 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 614 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1424 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 68944 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 26842 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 35344 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 131130 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6915 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 84458 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2264 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 30017 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 5904 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 49565 # number of demand (read+write) misses
-system.l2c.demand_misses::total 179170 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 6966 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 83404 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 31474 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 5226 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 49327 # number of demand (read+write) misses
+system.l2c.demand_misses::total 179263 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6915 # number of overall misses
-system.l2c.overall_misses::cpu0.data 84458 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2264 # number of overall misses
-system.l2c.overall_misses::cpu1.data 30017 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 5904 # number of overall misses
-system.l2c.overall_misses::cpu2.data 49565 # number of overall misses
-system.l2c.overall_misses::total 179170 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst 185117250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 320324250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3767000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 506409000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 1123352250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2138969750 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 5734849 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 6109808 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 11844657 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1967190465 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 2891355862 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 4858546327 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 185117250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 2287514715 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 3767000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 506409000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 4014708112 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 6997516077 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 185117250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 2287514715 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 3767000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 506409000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 4014708112 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 6997516077 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 19379 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 10647 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 302029 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 493869 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 12495 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 162655 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 224256 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 66692 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 14282 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 413272 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 629749 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2356711 # number of ReadReq accesses(hits+misses)
+system.l2c.overall_misses::cpu0.inst 6966 # number of overall misses
+system.l2c.overall_misses::cpu0.data 83404 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 2825 # number of overall misses
+system.l2c.overall_misses::cpu1.data 31474 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 35 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 5226 # number of overall misses
+system.l2c.overall_misses::cpu2.data 49327 # number of overall misses
+system.l2c.overall_misses::total 179263 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 229197000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 387947750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3073999 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 450638500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 1224001500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 2294941249 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 5739854 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 7551262 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 13291116 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 2024405687 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 2802525365 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 4826931052 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 229197000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 2412353437 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 3073999 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 450638500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 4026526865 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 7121872301 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 229197000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 2412353437 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 3073999 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 450638500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 4026526865 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 7121872301 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 19552 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 10774 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 294016 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 491215 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 13142 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 7558 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 171033 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 224470 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 66323 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 13297 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 406851 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 631176 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2349407 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 1546722 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1546722 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 745 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 313 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 585 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1643 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 126896 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 62255 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 101289 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 290440 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 19379 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 10649 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 302029 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 620765 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 12495 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 162655 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 286511 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 66692 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 14282 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 413272 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 731038 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2647153 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 19379 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 10649 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 302029 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 620765 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 12495 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 162655 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 286511 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 66692 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 14282 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 413272 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 731038 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2647153 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000470 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.022895 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.032600 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.013919 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.017208 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.014286 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.020791 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.020445 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.848322 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.821086 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.847863 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.842970 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.538693 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.420175 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.360079 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.450998 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000470 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.022895 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.136055 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.013919 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.104767 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.014286 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.067801 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.067684 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000470 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.022895 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.136055 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.013919 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.104767 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.014286 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.067801 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.067684 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81765.569788 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 83007.061415 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 85773.882114 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 85797.926373 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 44393.544270 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22314.587549 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12318.161290 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 8552.098917 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75204.161824 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79276.043595 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 37091.537599 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 39055.177078 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 39055.177078 # average overall miss latency
+system.l2c.Writeback_accesses::writebacks 1546428 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1546428 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 661 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 301 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 710 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 124931 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 62395 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 102700 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 290026 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 19552 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 10776 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 294016 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 616146 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 13142 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7558 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 171033 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 286865 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 66323 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 13297 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 406851 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 733876 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2639435 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 19552 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 10776 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 294016 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 616146 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 13142 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7558 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 171033 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 286865 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 66323 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 13297 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 406851 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 733876 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2639435 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000464 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.023693 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.029437 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.016517 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.020635 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.012845 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.022154 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.020487 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.841150 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.843854 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.864789 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.851675 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.551857 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.430195 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.344148 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.452132 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000464 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.023693 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.135364 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.016517 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.109717 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.012845 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.067214 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.067917 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000464 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.023693 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.135364 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.016517 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.109717 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.012845 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.067214 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.067917 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81131.681416 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 83753.832038 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.099502 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 87534.971036 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 47679.165001 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22597.850394 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12298.472313 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 9333.648876 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75419.331160 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79292.818159 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 36810.272645 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 39728.623871 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 39728.623871 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 96719 # number of writebacks
-system.l2c.writebacks::total 96719 # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst 2264 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 3859 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 5904 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 13093 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 25162 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 257 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 496 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 753 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 26158 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 36472 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 62630 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2264 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 30017 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 5904 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 49565 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 87792 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2264 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 30017 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 5904 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 49565 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 87792 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 156732750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 272024750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 432457000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 959731250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1824184750 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5165744 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8859994 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 14025738 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1640131535 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2435332138 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 4075463673 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 156732750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1912156285 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 432457000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 3395063388 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 5899648423 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 156732750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1912156285 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 432457000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 3395063388 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 5899648423 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27747826000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30174191500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 57922017500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 492354000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 747099000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 1239453000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28240180000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30921290500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 59161470500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017208 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020791 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.010677 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.821086 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847863 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.458308 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420175 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.360079 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.215638 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.033165 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.033165 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70490.995076 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73301.096005 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 72497.605516 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20100.171206 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17862.891129 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18626.478088 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62700.953246 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66772.651294 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 65072.068865 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency
+system.l2c.writebacks::writebacks 97053 # number of writebacks
+system.l2c.writebacks::total 97053 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 2825 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4632 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 35 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 5224 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 13983 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 26700 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 254 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 614 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 868 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 26842 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 35344 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 62186 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 2825 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 31474 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 35 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 5224 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 49327 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 88886 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 2825 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 31474 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 385025750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1049073500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1960621999 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5213239 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10949612 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 16162851 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1688636313 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2360590135 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 4049226448 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 193782500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 2018673563 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 385025750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 3409663635 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6009848447 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 193782500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 2018673563 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 385025750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 3409663635 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6009848447 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27827045500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30156785500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 57983831000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 554838500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 711575000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1266413500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28381884000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30868360500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 59250244500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020635 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022154 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.011365 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.843854 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.864789 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.519139 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430195 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344148 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.214415 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.033676 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.033676 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71251.565199 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 75024.923121 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 73431.535543 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20524.562992 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17833.244300 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18620.796083 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62910.226995 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66788.992050 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 65114.759721 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 5119167 # Transaction distribution
-system.membus.trans_dist::ReadResp 5119165 # Transaction distribution
-system.membus.trans_dist::WriteReq 13931 # Transaction distribution
-system.membus.trans_dist::WriteResp 13931 # Transaction distribution
-system.membus.trans_dist::Writeback 143386 # Transaction distribution
+system.membus.trans_dist::ReadReq 5117226 # Transaction distribution
+system.membus.trans_dist::ReadResp 5117226 # Transaction distribution
+system.membus.trans_dist::WriteReq 13905 # Transaction distribution
+system.membus.trans_dist::WriteResp 13905 # Transaction distribution
+system.membus.trans_dist::Writeback 143720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1652 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130721 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130721 # Transaction distribution
-system.membus.trans_dist::MessageReq 1679 # Transaction distribution
-system.membus.trans_dist::MessageResp 1679 # Transaction distribution
-system.membus.trans_dist::BadAddressError 2 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3358 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3358 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3041102 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457338 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10625356 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141623 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141623 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10770337 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569655 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6082201 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17609408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 27261264 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 6015616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 33283596 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 789 # Total snoops (count)
-system.membus.snoop_fanout::samples 371599 # Request fanout histogram
+system.membus.trans_dist::UpgradeReq 1707 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1707 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130847 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130847 # Transaction distribution
+system.membus.trans_dist::MessageReq 1698 # Transaction distribution
+system.membus.trans_dist::MessageResp 1698 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3396 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3396 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126806 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037388 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457961 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 10622155 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141555 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 141555 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10767106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074773 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17637504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 27281789 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 820 # Total snoops (count)
+system.membus.snoop_fanout::samples 372049 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 371599 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 372049 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 371599 # Request fanout histogram
-system.membus.reqLayer0.occupancy 233199000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 372049 # Request fanout histogram
+system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 303775500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 2272000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 2302000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 587213160 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 670380805 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1136000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1151000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1313776839 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1321113701 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 24877750 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 32422007 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 7456393 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7455858 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13933 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13933 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1546722 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 21038 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1643 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1643 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 290440 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 290440 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1755962 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14994862 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 74580 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 223072 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 17048476 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56190016 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213507600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 279632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823928 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 270801176 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 69805 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4272022 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011152 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.105014 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 7449528 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7448995 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13907 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13907 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1546428 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 28278 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 225048 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 17030802 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55802432 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213393597 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 72565 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4266300 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.011166 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.105077 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 4224379 98.88% 98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 47643 1.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 4218663 98.88% 98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 47637 1.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4272022 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2506180983 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4266300 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 318000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 865936683 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 868906655 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1938409360 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1944011740 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 26348986 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 26208491 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 96467647 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 98848126 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.062113 # Number of seconds simulated
-sim_ticks 62113055500 # Number of ticks simulated
-final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.062108 # Number of seconds simulated
+sim_ticks 62108139000 # Number of ticks simulated
+final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109820 # Simulator instruction rate (inst/s)
-host_op_rate 193376 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43175715 # Simulator tick rate (ticks/s)
-host_mem_usage 386160 # Number of bytes of host memory used
-host_seconds 1438.61 # Real time elapsed on the host
+host_inst_rate 88749 # Simulator instruction rate (inst/s)
+host_op_rate 156272 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34888646 # Simulator tick rate (ticks/s)
+host_mem_usage 448856 # Number of bytes of host memory used
+host_seconds 1780.18 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory
-system.physmem.bytes_written::total 10624 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 166 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30436 # Number of read requests accepted
-system.physmem.writeReqs 166 # Number of write requests accepted
-system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1951040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 13952 # Number of bytes written to this memory
+system.physmem.bytes_written::total 13952 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30485 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 218 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 218 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1045918 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 30367679 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 31413596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1045918 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1045918 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 224640 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 224640 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 224640 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1045918 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 30367679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 31638237 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30485 # Number of read requests accepted
+system.physmem.writeReqs 218 # Number of write requests accepted
+system.physmem.readBursts 30485 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 218 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
+system.physmem.bytesWritten 12736 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 1951040 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 13952 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1923 # Per bank write bursts
-system.physmem.perBankRdBursts::1 2063 # Per bank write bursts
+system.physmem.perBankRdBursts::0 1926 # Per bank write bursts
+system.physmem.perBankRdBursts::1 2065 # Per bank write bursts
system.physmem.perBankRdBursts::2 2030 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1928 # Per bank write bursts
-system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
+system.physmem.perBankRdBursts::3 1931 # Per bank write bursts
+system.physmem.perBankRdBursts::4 2028 # Per bank write bursts
system.physmem.perBankRdBursts::5 1903 # Per bank write bursts
system.physmem.perBankRdBursts::6 1964 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1866 # Per bank write bursts
+system.physmem.perBankRdBursts::7 1862 # Per bank write bursts
system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
-system.physmem.perBankRdBursts::9 1940 # Per bank write bursts
-system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
+system.physmem.perBankRdBursts::9 1938 # Per bank write bursts
+system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
system.physmem.perBankRdBursts::11 1795 # Per bank write bursts
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1818 # Per bank write bursts
+system.physmem.perBankRdBursts::14 1819 # Per bank write bursts
system.physmem.perBankRdBursts::15 1779 # Per bank write bursts
-system.physmem.perBankWrBursts::0 15 # Per bank write bursts
-system.physmem.perBankWrBursts::1 80 # Per bank write bursts
-system.physmem.perBankWrBursts::2 11 # Per bank write bursts
-system.physmem.perBankWrBursts::3 10 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::0 14 # Per bank write bursts
+system.physmem.perBankWrBursts::1 89 # Per bank write bursts
+system.physmem.perBankWrBursts::2 33 # Per bank write bursts
+system.physmem.perBankWrBursts::3 21 # Per bank write bursts
+system.physmem.perBankWrBursts::4 13 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7 # Per bank write bursts
system.physmem.perBankWrBursts::6 13 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6 # Per bank write bursts
system.physmem.perBankWrBursts::10 3 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 62113012500 # Total gap between requests
+system.physmem.totGap 62107943500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 30436 # Read request sizes (log2)
+system.physmem.readPktSize::6 30485 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 166 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 218 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 90 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
-system.physmem.totQLat 135350500 # Total ticks spent queuing
-system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 2733 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 715.170143 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 514.587482 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 389.057467 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 358 13.10% 13.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 248 9.07% 22.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 120 4.39% 26.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 119 4.35% 30.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 123 4.50% 35.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 99 3.62% 39.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 98 3.59% 42.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 77 2.82% 45.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 1491 54.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 2733 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 11 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2756.545455 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 17.211839 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 9104.288367 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 10 90.91% 90.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719 1 9.09% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 11 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 11 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.090909 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.068275 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.943880 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 1 9.09% 9.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 8 72.73% 81.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1 9.09% 90.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 1 9.09% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 11 # Writes before turning the bus around for reads
+system.physmem.totQLat 137229500 # Total ticks spent queuing
+system.physmem.totMemAccLat 706742000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 4517.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 23267.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 31.30 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 31.41 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.22 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.25 # Data bus utilization in percentage
system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing
-system.physmem.readRowHits 27681 # Number of row buffer hits during reads
-system.physmem.writeRowHits 96 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes
-system.physmem.avgGap 2029704.35 # Average gap between requests
-system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ)
-system.physmem_0.averagePower 673.255215 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states
+system.physmem.avgWrQLen 10.79 # Average write queue length when enqueuing
+system.physmem.readRowHits 27693 # Number of row buffer hits during reads
+system.physmem.writeRowHits 139 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 91.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
+system.physmem.avgGap 2022862.38 # Average gap between requests
+system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 10893960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 5944125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 1134000 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 2882954835 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 34733126250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 41812553730 # Total energy per rank (pJ)
+system.physmem_0.averagePower 673.273290 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 57766447750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 2264083750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 9699480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 5292375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 114270000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ)
-system.physmem_1.averagePower 673.417815 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states
+system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 3028786200 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 34605195750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 41819570205 # Total energy per rank (pJ)
+system.physmem_1.averagePower 673.386420 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 57553191500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 2477594500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 37409115 # Number of BP lookups
-system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits
+system.cpu.branchPred.lookups 37389273 # Number of BP lookups
+system.cpu.branchPred.condPredicted 37389273 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 796060 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 21398380 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21281300 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.452856 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 5538224 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5409 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 124226112 # number of cpu cycles simulated
+system.cpu.numCycles 124216279 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 28231712 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 201414270 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37389273 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 26819524 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 95072949 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1663625 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 13794 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 27828273 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 190340 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 124151097 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.859474 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.368729 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 63239379 50.94% 50.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3665567 2.95% 53.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3524262 2.84% 56.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5966051 4.81% 61.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7629037 6.14% 67.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5460577 4.40% 72.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3340077 2.69% 74.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2074079 1.67% 76.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 29252068 23.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 124151097 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.301001 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.621480 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 13268959 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 63731322 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 36520631 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9798373 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 831812 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 334996047 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 831812 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18591577 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8853243 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16711 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 40784813 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 55072941 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 328614087 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2150 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 765426 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 48317500 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4996682 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 330544508 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 872885571 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 537662987 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 823 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 478 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 47286965 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 51331761 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 491 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 491 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 66256508 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 106310670 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 36525048 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 49788623 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8449867 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 325445308 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 307970327 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 51339 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 47254612 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 68858955 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1323 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 124151097 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.480609 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.128122 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 30600533 24.65% 24.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19593175 15.78% 40.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 16755552 13.50% 53.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 17045170 13.73% 67.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 15962727 12.86% 80.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 12649852 10.19% 90.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5781799 4.66% 95.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4158736 3.35% 98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1603553 1.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 124151097 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 316480 7.51% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 3709774 87.98% 95.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 190338 4.51% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 175386232 56.95% 56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 347 0.00% 56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 45 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 98505322 31.99% 88.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 34033845 11.05% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued
-system.cpu.iq.rate 2.479264 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 372806758 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 722 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 307970327 # Type of FU issued
+system.cpu.iq.rate 2.479307 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 4216592 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013692 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 744358969 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 372741153 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 305973250 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 713 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1268 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 215 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 312153240 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 339 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 58265174 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 15531285 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 58585 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 41983 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 5085296 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3668 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 124310 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 831812 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5699246 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 3054980 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 325447076 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 123578 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 106310670 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 36525048 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2754 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3058247 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 41983 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 401587 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 444043 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 845630 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 306900581 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 98149248 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1069746 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31536553 # Number of branches executed
-system.cpu.iew.exec_stores 33820383 # Number of stores executed
-system.cpu.iew.exec_rate 2.470626 # Inst execution rate
-system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 231581512 # num instructions producing a value
-system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value
+system.cpu.iew.exec_refs 131968833 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31535132 # Number of branches executed
+system.cpu.iew.exec_stores 33819585 # Number of stores executed
+system.cpu.iew.exec_rate 2.470695 # Inst execution rate
+system.cpu.iew.wb_sent 306301702 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 305973465 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 231572201 # num instructions producing a value
+system.cpu.iew.wb_consumers 336082865 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.463232 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.689033 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 47355755 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 796864 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 117707358 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.363425 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 3.086682 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 53343112 45.32% 45.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 15934290 13.54% 58.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 11043478 9.38% 68.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8763951 7.45% 75.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1880549 1.60% 77.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1728612 1.47% 78.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 852753 0.72% 79.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 687313 0.58% 80.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 23473300 19.94% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 117707358 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
-system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 419820689 # The number of ROB reads
-system.cpu.rob.rob_writes 657620446 # The number of ROB writes
-system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 23473300 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 419782277 # The number of ROB reads
+system.cpu.rob.rob_writes 657549499 # The number of ROB writes
+system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 65182 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 493661924 # number of integer regfile reads
-system.cpu.int_regfile_writes 240899982 # number of integer regfile writes
-system.cpu.fp_regfile_reads 121 # number of floating regfile reads
-system.cpu.fp_regfile_writes 99 # number of floating regfile writes
-system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads
-system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes
-system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads
+system.cpu.cpi 0.786236 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.786236 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.271883 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.271883 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 493639930 # number of integer regfile reads
+system.cpu.int_regfile_writes 240886983 # number of integer regfile writes
+system.cpu.fp_regfile_reads 187 # number of floating regfile reads
+system.cpu.fp_regfile_writes 111 # number of floating regfile writes
+system.cpu.cc_regfile_reads 107695799 # number of cc regfile reads
+system.cpu.cc_regfile_writes 64567771 # number of cc regfile writes
+system.cpu.misc_regfile_reads 196286158 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2072451 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 2072438 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4067.873358 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 68418587 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2076534 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 32.948455 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 19755616250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4067.873358 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993133 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993133 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 606 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits
-system.cpu.dcache.overall_hits::total 68431233 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses
-system.cpu.dcache.overall_misses::total 2779048 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 144472022 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 144472022 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 37072750 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 37072750 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31345837 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31345837 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 68418587 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 68418587 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 68418587 # number of overall hits
+system.cpu.dcache.overall_hits::total 68418587 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2685242 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2685242 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 93915 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 93915 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2779157 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2779157 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2779157 # number of overall misses
+system.cpu.dcache.overall_misses::total 2779157 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 32132974500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 32132974500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2979596244 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2979596244 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 35112570744 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35112570744 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35112570744 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35112570744 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 39757992 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 39757992 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 71197744 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 71197744 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 71197744 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 71197744 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067540 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.067540 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.039034 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.039034 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.039034 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.039034 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11966.509722 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11966.509722 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31726.521259 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31726.521259 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12634.252309 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12634.252309 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 199012 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 39951 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.981402 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks
-system.cpu.dcache.writebacks::total 2066749 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks 2066723 # number of writebacks
+system.cpu.dcache.writebacks::total 2066723 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690734 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 690734 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11889 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 11889 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 702623 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 702623 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 702623 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 702623 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82026 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 82026 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2076534 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2076534 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2076534 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2076534 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23036962750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 23036962750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2767409747 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2767409747 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25804372497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 25804372497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25804372497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 25804372497 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050166 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.029166 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.029166 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11550.198219 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11550.198219 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33738.201875 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33738.201875 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 58 # number of replacements
-system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 61 # number of replacements
+system.cpu.icache.tags.tagsinuse 828.295860 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 27826925 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 26964.074612 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 832.593358 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.406540 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.406540 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 970 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits
-system.cpu.icache.overall_hits::total 27843840 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1337 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1337 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1337 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1337 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1337 # number of overall misses
-system.cpu.icache.overall_misses::total 1337 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 100311747 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 100311747 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 100311747 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 100311747 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 100311747 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 100311747 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 27845177 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 27845177 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 27845177 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 27845177 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 27845177 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 27845177 # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 828.295860 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.404441 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.404441 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 971 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 55657578 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 55657578 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 27826925 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 27826925 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 27826925 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 27826925 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 27826925 # number of overall hits
+system.cpu.icache.overall_hits::total 27826925 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses
+system.cpu.icache.overall_misses::total 1348 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 101838000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 101838000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 101838000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 101838000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 101838000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 101838000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 27828273 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 27828273 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 27828273 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 27828273 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 27828273 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 27828273 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75027.484667 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75027.484667 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75027.484667 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75027.484667 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 601 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75547.477745 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75547.477745 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75547.477745 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75547.477745 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 100.166667 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 65.714286 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1028 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1028 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1028 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1028 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79616501 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 79616501 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79616501 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 79616501 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79616501 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 79616501 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 316 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 316 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 316 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 316 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 316 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1032 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1032 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1032 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1032 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79628000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 79628000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79628000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 79628000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79628000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 79628000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77447.958171 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77447.958171 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77158.914729 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77158.914729 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 480 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 20677.307711 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4029650 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 30419 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 132.471482 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 538 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 20666.246528 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 4029584 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 30468 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 132.256269 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19740.626067 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 685.734645 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 250.946999 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.602436 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020927 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.007658 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.631021 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29939 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 2066749 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 53083 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 53083 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2047126 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2047140 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2047126 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2047140 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 1014 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1440 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1014 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 30436 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1014 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses
-system.cpu.l2cache.overall_misses::total 30436 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78434000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32404750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 110838750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2126346500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2126346500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 78434000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 19735.717882 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.212002 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 249.316644 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.602286 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020789 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.007609 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.630684 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29930 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 808 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1396 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27603 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913391 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 33266846 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 33266846 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1994001 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1994018 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2066723 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2066723 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 53063 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 53063 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2047064 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2047081 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2047064 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2047081 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 1015 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 467 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1482 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 1015 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 29470 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 30485 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 1015 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 29470 # number of overall misses
+system.cpu.l2cache.overall_misses::total 30485 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78409250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34652250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 113061500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2128130000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2128130000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 78409250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 2162782250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 2241191500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 78409250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 2162782250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 2241191500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1032 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1994468 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1995500 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2066723 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2066723 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 82066 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 82066 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2076534 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2077566 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2076534 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2077566 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983527 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000234 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.000743 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353411 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.353411 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983527 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014192 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.014673 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983527 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014192 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.014673 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77250.492611 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74201.820128 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76289.811066 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73376.202462 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73376.202462 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73517.844842 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73517.844842 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks
-system.cpu.l2cache.writebacks::total 166 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 218 # number of writebacks
+system.cpu.l2cache.writebacks::total 218 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1482 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29470 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 30485 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29470 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 30485 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65734750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28861750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94596500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1765566500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1765566500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65734750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1794428250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1860163000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65734750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1794428250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1860163000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000743 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353411 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353411 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014673 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014673 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64763.300493 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61802.462527 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63830.296896 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60875.306003 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60875.306003 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 1995500 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1995500 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2066723 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 82066 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 82066 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2064 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219791 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6221855 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265168448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4144289 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1740500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3121586499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 1440 # Transaction distribution
-system.membus.trans_dist::ReadResp 1439 # Transaction distribution
-system.membus.trans_dist::Writeback 166 # Transaction distribution
-system.membus.trans_dist::ReadExReq 28996 # Transaction distribution
-system.membus.trans_dist::ReadExResp 28996 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 1482 # Transaction distribution
+system.membus.trans_dist::ReadResp 1482 # Transaction distribution
+system.membus.trans_dist::Writeback 218 # Transaction distribution
+system.membus.trans_dist::ReadExReq 29003 # Transaction distribution
+system.membus.trans_dist::ReadExResp 29003 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61188 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61188 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 61188 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1964992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1964992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1964992 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 30602 # Request fanout histogram
+system.membus.snoop_fanout::samples 30703 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 30703 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 30602 # Request fanout histogram
-system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 30703 # Request fanout histogram
+system.membus.reqLayer0.occupancy 42842500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 160650000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.455715 # Number of seconds simulated
-sim_ticks 455715234500 # Number of ticks simulated
-final_tick 455715234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.417785 # Number of seconds simulated
+sim_ticks 417784645500 # Number of ticks simulated
+final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95556 # Simulator instruction rate (inst/s)
-host_op_rate 176693 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52663419 # Simulator tick rate (ticks/s)
-host_mem_usage 364636 # Number of bytes of host memory used
-host_seconds 8653.35 # Real time elapsed on the host
+host_inst_rate 77548 # Simulator instruction rate (inst/s)
+host_op_rate 143396 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39181823 # Simulator tick rate (ticks/s)
+host_mem_usage 423644 # Number of bytes of host memory used
+host_seconds 10662.72 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 225856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24534720 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24760576 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 225856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 225856 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18815424 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18815424 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3529 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383355 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386884 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293991 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293991 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 495608 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 53837831 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54333439 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 495608 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 495608 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 41287678 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 41287678 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 41287678 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 495608 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 53837831 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 95621118 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386885 # Number of read requests accepted
-system.physmem.writeReqs 293991 # Number of write requests accepted
-system.physmem.readBursts 386885 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 293991 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24739328 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18814144 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24760640 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18815424 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386904 # Number of read requests accepted
+system.physmem.writeReqs 294034 # Number of write requests accepted
+system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 191853 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24085 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26442 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24611 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24606 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23306 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23756 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24486 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24652 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23681 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23594 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24798 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24113 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26506 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24704 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24585 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23284 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23758 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23622 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
system.physmem.perBankRdBursts::11 24077 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23369 # Per bank write bursts
-system.physmem.perBankRdBursts::13 23004 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24109 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23976 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18564 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19853 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18919 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18930 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18043 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18450 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18985 # Per bank write bursts
-system.physmem.perBankWrBursts::7 19190 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18567 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17917 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18839 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17726 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17379 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16983 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17822 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17804 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23364 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22990 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24090 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23971 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18545 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19845 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18943 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18938 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18456 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18996 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18987 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18549 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18172 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18834 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17732 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16972 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17820 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17802 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 455715219000 # Total gap between requests
+system.physmem.totGap 417784619000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386885 # Read request sizes (log2)
+system.physmem.readPktSize::6 386904 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 293991 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381599 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4552 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 347 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294034 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17476 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17572 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17558 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17577 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17595 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17611 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17644 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17591 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17646 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17535 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17475 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147989 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 294.299928 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 173.923079 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 321.799681 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54958 37.14% 37.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40521 27.38% 64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13835 9.35% 73.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7266 4.91% 78.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5442 3.68% 82.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4031 2.72% 85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3118 2.11% 87.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2726 1.84% 89.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16092 10.87% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147989 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.176123 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 209.527519 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17419 99.93% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17430 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.865060 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.791911 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.512995 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17223 98.81% 98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 149 0.85% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 30 0.17% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 9 0.05% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 3 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17430 # Writes before turning the bus around for reads
-system.physmem.totQLat 4293065000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11540915000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1932760000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11106.02 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29855.97 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 54.29 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 41.28 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 54.33 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 41.29 # Average system write bandwidth in MiByte/s
+system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads
+system.physmem.totQLat 4274781750 # Total ticks spent queuing
+system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.75 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing
-system.physmem.readRowHits 317463 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215067 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
-system.physmem.avgGap 669307.21 # Average gap between requests
-system.physmem.pageHitRate 78.25 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 572420520 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 312332625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1528355400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 977968080 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 29764999680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 65726366265 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 215773632750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 314656075320 # Total energy per rank (pJ)
-system.physmem_0.averagePower 690.468461 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 358390621750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 15217280000 # Time in different power states
+system.physmem.busUtil 0.81 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing
+system.physmem.readRowHits 318043 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215127 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes
+system.physmem.avgGap 613542.82 # Average gap between requests
+system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ)
+system.physmem_0.averagePower 692.139218 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 82106088250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 546247800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 298051875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1486602000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 926776080 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 29764999680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 63297439515 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 217904270250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 314224387200 # Total energy per rank (pJ)
-system.physmem_1.averagePower 689.521182 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 361949321250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 15217280000 # Time in different power states
+system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ)
+system.physmem_1.averagePower 691.288514 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 78547312500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 231695087 # Number of BP lookups
-system.cpu.branchPred.condPredicted 231695087 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9749161 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 132117764 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 129359921 # Number of BTB hits
+system.cpu.branchPred.lookups 230228501 # Number of BP lookups
+system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.912587 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 28019082 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1472513 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 911430498 # number of cpu cycles simulated
+system.cpu.numCycles 835569292 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 186296226 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1278949517 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 231695087 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 157379003 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 713875771 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20236911 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 843 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 99453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 835728 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1660 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 72 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 180582964 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2713511 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 911228208 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.609913 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.335178 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 500401689 54.92% 54.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 34125690 3.75% 58.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 33332463 3.66% 62.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 33617134 3.69% 66.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27404429 3.01% 69.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 27784633 3.05% 72.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 37330287 4.10% 76.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33792897 3.71% 79.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183438986 20.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 911228208 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.254210 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.403233 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127697766 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 450696701 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 239651398 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 83063888 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10118455 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2233614820 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 10118455 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 159982570 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 230664398 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 40764 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 285690426 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 224731595 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2183551679 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 177689 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 141075901 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24311507 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 48530126 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2288986524 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5525749346 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3513986925 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 64934 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 674945670 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3353 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3126 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 428782866 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 530734595 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 210445129 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 240719653 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 72347559 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2112788093 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 24468 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1829137533 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 426447 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 583823860 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1007575077 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 23916 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 911228208 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.007332 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.067633 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 325992359 35.78% 35.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 131250522 14.40% 50.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 120537234 13.23% 63.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 111169469 12.20% 75.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 91475128 10.04% 85.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 61217160 6.72% 92.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 43196755 4.74% 97.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 18979354 2.08% 99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7410227 0.81% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 911228208 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11335968 42.56% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12226894 45.90% 88.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3075179 11.54% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2719775 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1213037771 66.32% 66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 388267 0.02% 66.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880871 0.21% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 112 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 48 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 465 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 435424012 23.80% 90.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 173686212 9.50% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1829137533 # Type of FU issued
-system.cpu.iq.rate 2.006886 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26638041 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014563 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4596535787 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2696900293 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1799537822 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 31975 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 69902 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6901 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1853040947 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 14852 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185563330 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued
+system.cpu.iq.rate 2.186445 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 146635930 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 210802 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 388472 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 61284943 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 18850 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 952 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10118455 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 169584093 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10386937 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2112812561 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 394512 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 530738087 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 210445129 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7053 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4503089 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3731660 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 388472 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5744189 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4593759 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10337948 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1808033307 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 429361199 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21104226 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 599489274 # number of memory reference insts executed
-system.cpu.iew.exec_branches 171937546 # Number of branches executed
-system.cpu.iew.exec_stores 170128075 # Number of stores executed
-system.cpu.iew.exec_rate 1.983731 # Inst execution rate
-system.cpu.iew.wb_sent 1804836297 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1799544723 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1369264226 # num instructions producing a value
-system.cpu.iew.wb_consumers 2092761334 # num instructions consuming a value
+system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171787473 # Number of branches executed
+system.cpu.iew.exec_stores 170142360 # Number of stores executed
+system.cpu.iew.exec_rate 2.160793 # Inst execution rate
+system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1368063103 # num instructions producing a value
+system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.974418 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 584053108 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9837261 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 832077003 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.837557 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.497071 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 362943344 43.62% 43.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 175693429 21.12% 64.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 57310072 6.89% 71.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86390127 10.38% 82.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 27179123 3.27% 85.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27109381 3.26% 88.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9762579 1.17% 89.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8845708 1.06% 90.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 76843240 9.24% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 832077003 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 76843240 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2868275572 # The number of ROB reads
-system.cpu.rob.rob_writes 4305421890 # The number of ROB writes
-system.cpu.timesIdled 2629 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 202290 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 2781912801 # The number of ROB reads
+system.cpu.rob.rob_writes 4280130406 # The number of ROB writes
+system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.102256 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.102256 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.907230 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.907230 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2763463473 # number of integer regfile reads
-system.cpu.int_regfile_writes 1467615781 # number of integer regfile writes
-system.cpu.fp_regfile_reads 7179 # number of floating regfile reads
-system.cpu.fp_regfile_writes 441 # number of floating regfile writes
-system.cpu.cc_regfile_reads 600951276 # number of cc regfile reads
-system.cpu.cc_regfile_writes 409693961 # number of cc regfile writes
-system.cpu.misc_regfile_reads 991720731 # number of misc regfile reads
+system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads
+system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes
+system.cpu.fp_regfile_reads 7481 # number of floating regfile reads
+system.cpu.fp_regfile_writes 493 # number of floating regfile writes
+system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads
+system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes
+system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2532518 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4088.661230 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 388324970 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2536614 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 153.087924 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 2534249 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4088.661230 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998208 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998208 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 783 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3267 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 785768584 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 785768584 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 239673208 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 239673208 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148177372 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148177372 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 387850580 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 387850580 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 387850580 # number of overall hits
-system.cpu.dcache.overall_hits::total 387850580 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2782575 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2782575 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 982830 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 982830 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3765405 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3765405 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3765405 # number of overall misses
-system.cpu.dcache.overall_misses::total 3765405 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 60028359597 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 60028359597 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31203952015 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31203952015 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 91232311612 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 91232311612 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 91232311612 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 91232311612 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 242455783 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 242455783 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits
+system.cpu.dcache.overall_hits::total 387338908 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses
+system.cpu.dcache.overall_misses::total 3776174 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 391615985 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 391615985 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 391615985 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 391615985 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011477 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011477 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006589 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006589 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009615 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009615 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009615 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009615 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21572.952965 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21572.952965 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31749.083784 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31749.083784 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24229.083355 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24229.083355 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24229.083355 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24229.083355 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 10901 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.000917 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 2.500000 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2331746 # number of writebacks
-system.cpu.dcache.writebacks::total 2331746 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016736 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1016736 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18354 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18354 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1035090 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1035090 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1035090 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1035090 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765839 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1765839 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964476 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 964476 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2730315 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2730315 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2730315 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2730315 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32758208252 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 32758208252 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29421929982 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 29421929982 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62180138234 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 62180138234 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62180138234 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 62180138234 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007283 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007283 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006466 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006466 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006972 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006972 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006972 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006972 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18551.073032 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18551.073032 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30505.611318 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30505.611318 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.979645 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.979645 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.979645 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.979645 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks
+system.cpu.dcache.writebacks::total 2332976 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 7158 # number of replacements
-system.cpu.icache.tags.tagsinuse 1086.852590 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 180374777 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 8766 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 20576.634383 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 7023 # number of replacements
+system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1086.852590 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.530690 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.530690 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 291 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1188 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 361368535 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 361368535 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 180377818 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 180377818 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 180377818 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 180377818 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 180377818 # number of overall hits
-system.cpu.icache.overall_hits::total 180377818 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 205146 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 205146 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 205146 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 205146 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 205146 # number of overall misses
-system.cpu.icache.overall_misses::total 205146 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1309293240 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1309293240 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1309293240 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1309293240 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1309293240 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1309293240 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 180582964 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 180582964 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 180582964 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 180582964 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 180582964 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 180582964 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001136 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001136 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.001136 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.001136 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.001136 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.001136 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6382.250885 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6382.250885 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 6382.250885 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 6382.250885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6382.250885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6382.250885 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1556 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits
+system.cpu.icache.overall_hits::total 179276307 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses
+system.cpu.icache.overall_misses::total 208110 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 67.652174 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2537 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2537 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2537 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2537 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2537 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2537 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202609 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 202609 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 202609 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 202609 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 202609 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 202609 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 890830010 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 890830010 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 890830010 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 890830010 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 890830010 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 890830010 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001122 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001122 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001122 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.001122 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001122 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.001122 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4396.793874 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4396.793874 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4396.793874 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 4396.793874 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4396.793874 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 4396.793874 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 354201 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 29695.160220 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3700802 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 386532 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 9.574374 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 197848612000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21110.060927 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 253.708059 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.391234 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.644228 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007743 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.254254 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.906224 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32331 # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements 354223 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11729 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20298 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986664 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 41726644 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 41726644 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 5259 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1589230 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1594489 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 2331746 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 2331746 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1880 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1880 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 563997 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 563997 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 5259 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2153227 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2158486 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 5259 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2153227 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2158486 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3532 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 176392 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 179924 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 191821 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 191821 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 206995 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 206995 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3532 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 383387 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 386919 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3532 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 383387 # number of overall misses
-system.cpu.l2cache.overall_misses::total 386919 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 291122000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14268096000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 14559218000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13253076 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 13253076 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16447945218 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 16447945218 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 291122000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 30716041218 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 31007163218 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 291122000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 30716041218 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 31007163218 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 8791 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1765622 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1774413 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 2331746 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 2331746 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193701 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 193701 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 770992 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 770992 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 8791 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2536614 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2545405 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 8791 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2536614 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2545405 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.401775 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099904 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.101399 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990294 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990294 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268479 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.268479 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.401775 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.151141 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.152007 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.401775 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.151141 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.152007 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82424.122310 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80888.566375 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80918.710122 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.090850 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.090850 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79460.591889 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79460.591889 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82424.122310 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80117.586715 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80138.641984 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82424.122310 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80117.586715 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80138.641984 # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18671 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 41773644 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 41773644 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 5119 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1590451 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1595570 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2332976 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2332976 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 1900 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 1900 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 564474 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 564474 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 5119 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2154925 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2160044 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 5119 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2154925 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2160044 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3526 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 176410 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 179936 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 194792 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 194792 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 207010 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 207010 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3526 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 383420 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 386946 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3526 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 383420 # number of overall misses
+system.cpu.l2cache.overall_misses::total 386946 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 288437750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275708250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 14564146000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12898587 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 12898587 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16427155710 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 16427155710 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 288437750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 30702863960 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 30991301710 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 288437750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 30702863960 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 30991301710 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 8645 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1766861 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1775506 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2332976 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2332976 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196692 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 196692 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 771484 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 771484 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 8645 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2538345 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2546990 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 8645 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2538345 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2546990 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407866 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099844 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.101344 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990340 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990340 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268327 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.268327 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407866 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.151051 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.151923 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407866 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.151051 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.151923 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81803.105502 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80923.463806 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 80940.701138 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.217232 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.217232 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79354.406599 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79354.406599 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80092.058608 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80092.058608 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 293991 # number of writebacks
-system.cpu.l2cache.writebacks::total 293991 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 294034 # number of writebacks
+system.cpu.l2cache.writebacks::total 294034 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3531 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176392 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 179923 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 191821 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 191821 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206995 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 206995 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3531 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 383387 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 386918 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3531 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 383387 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 386918 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 246937500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12060771500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12307709000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3460977638 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3460977638 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13859464782 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13859464782 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246937500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25920236282 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26167173782 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246937500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25920236282 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26167173782 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.401661 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099904 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101399 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990294 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990294 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268479 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268479 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.401661 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151141 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.152006 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.401661 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151141 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.152006 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69934.154630 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68374.821420 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68405.423431 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18042.746300 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18042.746300 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66955.553429 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66955.553429 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69934.154630 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.542496 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67629.765950 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69934.154630 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.542496 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67629.765950 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3525 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176410 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 179935 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194792 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 194792 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207010 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 207010 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3525 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 383420 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 386945 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3525 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 383420 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 386945 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 244319250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068297250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12312616500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3517284221 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3517284221 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13838517790 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13838517790 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244319250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25906815040 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26151134290 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244319250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25906815040 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26151134290 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099844 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101343 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990340 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990340 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268327 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268327 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.151922 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 1968231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1968229 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2331746 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 193701 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 193701 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 770992 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 770992 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 211398 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7792376 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8003774 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 562496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311575040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312137536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 193818 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 5264670 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 196816 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 5264670 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5264670 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4991624303 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 304450990 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3984789765 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 179922 # Transaction distribution
-system.membus.trans_dist::ReadResp 179921 # Transaction distribution
-system.membus.trans_dist::Writeback 293991 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 191853 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 191853 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206963 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206963 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1451466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1451466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1451466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43576000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43576000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43576000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 179934 # Transaction distribution
+system.membus.trans_dist::ReadResp 179934 # Transaction distribution
+system.membus.trans_dist::Writeback 294034 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206970 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206970 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 872729 # Request fanout histogram
+system.membus.snoop_fanout::samples 875770 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 872729 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 872729 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2240390129 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 875770 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2431381451 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.148669 # Number of seconds simulated
-sim_ticks 148668850500 # Number of ticks simulated
-final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.081225 # Number of seconds simulated
+sim_ticks 81224844500 # Number of ticks simulated
+final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74389 # Simulator instruction rate (inst/s)
-host_op_rate 124683 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 83737935 # Simulator tick rate (ticks/s)
-host_mem_usage 279976 # Number of bytes of host memory used
-host_seconds 1775.41 # Real time elapsed on the host
+host_inst_rate 72712 # Simulator instruction rate (inst/s)
+host_op_rate 121872 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44718419 # Simulator tick rate (ticks/s)
+host_mem_usage 340792 # Number of bytes of host memory used
+host_seconds 1816.36 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory
-system.physmem.bytes_read::total 350848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5482 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 350528 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5477 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2767232 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1548295 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4315527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2767232 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2767232 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2767232 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1548295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4315527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5477 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 5477 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 350528 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 350528 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 294 # Per bank write bursts
-system.physmem.perBankRdBursts::1 364 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 298 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 295 # Per bank write bursts
+system.physmem.perBankRdBursts::1 355 # Per bank write bursts
system.physmem.perBankRdBursts::2 457 # Per bank write bursts
-system.physmem.perBankRdBursts::3 371 # Per bank write bursts
-system.physmem.perBankRdBursts::4 339 # Per bank write bursts
-system.physmem.perBankRdBursts::5 333 # Per bank write bursts
-system.physmem.perBankRdBursts::6 398 # Per bank write bursts
-system.physmem.perBankRdBursts::7 383 # Per bank write bursts
-system.physmem.perBankRdBursts::8 344 # Per bank write bursts
-system.physmem.perBankRdBursts::9 280 # Per bank write bursts
-system.physmem.perBankRdBursts::10 239 # Per bank write bursts
-system.physmem.perBankRdBursts::11 268 # Per bank write bursts
-system.physmem.perBankRdBursts::12 225 # Per bank write bursts
-system.physmem.perBankRdBursts::13 502 # Per bank write bursts
+system.physmem.perBankRdBursts::3 353 # Per bank write bursts
+system.physmem.perBankRdBursts::4 337 # Per bank write bursts
+system.physmem.perBankRdBursts::5 331 # Per bank write bursts
+system.physmem.perBankRdBursts::6 400 # Per bank write bursts
+system.physmem.perBankRdBursts::7 389 # Per bank write bursts
+system.physmem.perBankRdBursts::8 346 # Per bank write bursts
+system.physmem.perBankRdBursts::9 296 # Per bank write bursts
+system.physmem.perBankRdBursts::10 240 # Per bank write bursts
+system.physmem.perBankRdBursts::11 297 # Per bank write bursts
+system.physmem.perBankRdBursts::12 220 # Per bank write bursts
+system.physmem.perBankRdBursts::13 472 # Per bank write bursts
system.physmem.perBankRdBursts::14 395 # Per bank write bursts
-system.physmem.perBankRdBursts::15 290 # Per bank write bursts
+system.physmem.perBankRdBursts::15 294 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 148668756000 # Total gap between requests
+system.physmem.totGap 81224754500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5482 # Read request sizes (log2)
+system.physmem.readPktSize::6 5477 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4344 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 912 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 189 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation
-system.physmem.totQLat 40930250 # Total ticks spent queuing
-system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1132 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 308.296820 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 177.870491 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.897635 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 457 40.37% 40.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 236 20.85% 61.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 108 9.54% 70.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 58 5.12% 75.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 52 4.59% 80.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 57 5.04% 85.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 15 1.33% 86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 18 1.59% 88.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 131 11.57% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1132 # Bytes accessed per row activation
+system.physmem.totQLat 39829000 # Total ticks spent queuing
+system.physmem.totMemAccLat 142522750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 27385000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7272.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26022.05 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4334 # Number of row buffer hits during reads
+system.physmem.readRowHits 4337 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 27119437.43 # Average gap between requests
-system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 14830154.19 # Average gap between requests
+system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4944240 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2697750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 22612200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.842708 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states
+system.physmem_0.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 2574291285 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 46473030000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 54382364835 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.579902 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 77308994750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 2712060000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1198731250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 3598560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1963500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 19773000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.641253 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states
+system.physmem_1.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 2411784000 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 46615580250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 54357488670 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.273616 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 77550451000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 2712060000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 960225000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 22385702 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits
+system.cpu.branchPred.lookups 21757824 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21757824 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1548941 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 13682195 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 12857487 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.972400 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1522808 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 297337717 # number of cpu cycles simulated
+system.cpu.numCycles 162449690 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 27167357 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 241462052 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 21757824 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 14380295 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 133204520 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3672137 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 11 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 3242 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 32817 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 121 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 26014450 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 320059 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 162244149 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.449323 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.349447 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 96544935 59.51% 59.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4966288 3.06% 62.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3924303 2.42% 64.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4589791 2.83% 67.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4444336 2.74% 70.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5042325 3.11% 73.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5076481 3.13% 76.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3889378 2.40% 79.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 33766312 20.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 162244149 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.133936 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.486381 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16503411 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96610290 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 25882430 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 21411950 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1836068 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 352729241 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1836068 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 24442767 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 33233774 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 31009 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 38303751 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 64396780 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 343252745 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1943 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 56953505 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 7545423 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 167940 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 397342568 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 949709399 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 627052131 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4618257 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 119976250 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 137913118 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2151 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2060 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 120010907 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 87039709 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 31137080 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 61853756 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 20927707 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 331596276 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4834 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 264603975 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 77857 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 110237726 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 225639096 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3589 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 162244149 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.630900 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.539803 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 42788422 26.37% 26.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 47622129 29.35% 55.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 33320454 20.54% 76.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18328192 11.30% 87.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 11302199 6.97% 94.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4922011 3.03% 97.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2609014 1.61% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 930397 0.57% 99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 421331 0.26% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 162244149 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 230632 7.18% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2590896 80.61% 87.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 392432 12.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1211493 0.46% 0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 165364025 62.49% 62.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 786761 0.30% 63.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7038559 2.66% 65.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1211557 0.46% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 66257169 25.04% 91.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 22734411 8.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued
-system.cpu.iq.rate 0.897488 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 457303449 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4335295 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 264603975 # Type of FU issued
+system.cpu.iq.rate 1.628836 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3213960 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 689757647 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 437892717 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 258330357 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 4986269 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4261617 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2393080 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 264097165 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2509277 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 18796485 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 30390155 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14027 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 322538 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10621363 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 52082 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1836068 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 14114838 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 500285 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 331601110 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 108836 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 87039742 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 31137080 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2060 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 401860 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 61208 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 322538 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 680213 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 929259 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1609472 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 262268386 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 65330198 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2335589 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14589088 # Number of branches executed
-system.cpu.iew.exec_stores 22597595 # Number of stores executed
-system.cpu.iew.exec_rate 0.890361 # Inst execution rate
-system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 208896510 # num instructions producing a value
-system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value
+system.cpu.iew.exec_refs 87858182 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14520351 # Number of branches executed
+system.cpu.iew.exec_stores 22527984 # Number of stores executed
+system.cpu.iew.exec_rate 1.614459 # Inst execution rate
+system.cpu.iew.wb_sent 261554043 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 260723437 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 208617070 # num instructions producing a value
+system.cpu.iew.wb_consumers 375029707 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.604949 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.556268 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 110244875 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1552031 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147195030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.503878 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.943897 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 47434016 32.23% 32.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57618157 39.14% 71.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14262797 9.69% 81.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11889308 8.08% 89.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4213027 2.86% 92.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2877009 1.95% 93.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 914800 0.62% 94.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1061572 0.72% 95.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6924344 4.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 147195030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 615300578 # The number of ROB reads
-system.cpu.rob.rob_writes 699132843 # The number of ROB writes
-system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 6924344 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 471878945 # The number of ROB reads
+system.cpu.rob.rob_writes 678308439 # The number of ROB writes
+system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 205541 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 456486870 # number of integer regfile reads
-system.cpu.int_regfile_writes 239256029 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes
-system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads
-system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes
-system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads
+system.cpu.cpi 1.230016 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.230016 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.812998 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.812998 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 454025160 # number of integer regfile reads
+system.cpu.int_regfile_writes 236935746 # number of integer regfile writes
+system.cpu.fp_regfile_reads 3267968 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2053127 # number of floating regfile writes
+system.cpu.cc_regfile_reads 102766500 # number of cc regfile reads
+system.cpu.cc_regfile_writes 60037026 # number of cc regfile writes
+system.cpu.misc_regfile_reads 135494920 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 51 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 56 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1448.236298 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 66889390 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2008 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33311.449203 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits
-system.cpu.dcache.overall_hits::total 67084214 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses
-system.cpu.dcache.overall_misses::total 2936 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data 1448.236298 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.353573 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.353573 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1952 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.476562 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 133785736 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 133785736 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 46375033 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 46375033 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20513891 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20513891 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 66888924 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 66888924 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 66888924 # number of overall hits
+system.cpu.dcache.overall_hits::total 66888924 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1100 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1100 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1840 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1840 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2940 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2940 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2940 # number of overall misses
+system.cpu.dcache.overall_misses::total 2940 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 68941167 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 68941167 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 128874548 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 128874548 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 197815715 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 197815715 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 197815715 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 197815715 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 46376133 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 46376133 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 66891864 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 66891864 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 66891864 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 66891864 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62673.788182 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62673.788182 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70040.515217 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70040.515217 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67284.256803 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67284.256803 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
-system.cpu.dcache.writebacks::total 10 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
+system.cpu.dcache.writebacks::total 13 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1839 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1839 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2307 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2307 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2307 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2307 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36256250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36256250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125371702 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 125371702 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161627952 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 161627952 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161627952 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 161627952 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77470.619658 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77470.619658 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68173.845568 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68173.845568 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 5861 # number of replacements
-system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 5865 # number of replacements
+system.cpu.icache.tags.tagsinuse 1646.159130 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 26003921 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 7839 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3317.249777 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits
-system.cpu.icache.overall_hits::total 26645946 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses
-system.cpu.icache.overall_misses::total 10610 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1646.159130 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.803789 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.803789 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1974 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 898 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 773 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.963867 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 52037036 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 52037036 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 26003921 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 26003921 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 26003921 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 26003921 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 26003921 # number of overall hits
+system.cpu.icache.overall_hits::total 26003921 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 10528 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 10528 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 10528 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 10528 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 10528 # number of overall misses
+system.cpu.icache.overall_misses::total 10528 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 430452747 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 430452747 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 430452747 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 430452747 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 430452747 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 430452747 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 26014449 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 26014449 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 26014449 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 26014449 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 26014449 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 26014449 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000405 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000405 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000405 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000405 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000405 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000405 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40886.469130 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 40886.469130 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 40886.469130 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 40886.469130 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1891 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 67.535714 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2389 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2389 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2389 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2389 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2389 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2389 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8139 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 8139 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 8139 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 8139 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 8139 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 8139 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322188751 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 322188751 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322188751 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 322188751 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322188751 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 322188751 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39585.790761 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39585.790761 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 2629.714027 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 4366 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 3947 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 1.106157 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
-system.cpu.l2cache.overall_hits::total 4354 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 2.821104 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2311.277195 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 315.615728 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000086 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070535 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.009632 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.080253 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 3947 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1031 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2655 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120453 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 86769 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 86769 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 4327 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 4362 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 4327 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 4370 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 4327 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits
+system.cpu.l2cache.overall_hits::total 4370 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3513 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 432 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3945 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses
-system.cpu.l2cache.overall_misses::total 5483 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst 3513 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1965 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 5478 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3513 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1965 # number of overall misses
+system.cpu.l2cache.overall_misses::total 5478 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 268162500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35336500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 303499000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114204250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 114204250 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 268162500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 149540750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 417703250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 268162500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 149540750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 417703250 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 7840 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 467 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 8307 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 299 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 299 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 7840 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2008 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9848 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 7840 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2008 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9848 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448087 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.925054 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.474901 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996656 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996656 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994809 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.994809 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448087 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.978586 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.556255 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448087 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.978586 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.556255 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76334.329633 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81797.453704 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76932.572877 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74497.227658 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74497.227658 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76334.329633 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76102.162850 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76251.049653 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76334.329633 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76102.162850 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76251.049653 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 432 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3945 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1965 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5478 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1965 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5478 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 224321500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29932000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 254253500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5280798 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5280798 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95023750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95023750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 224321500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124955750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 349277250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 224321500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124955750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 349277250 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925054 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474901 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996656 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996656 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994809 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994809 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978586 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.556255 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978586 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.556255 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63854.682607 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69287.037037 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64449.556401 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17720.798658 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17720.798658 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61985.485975 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61985.485975 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63854.682607 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.712468 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63759.994524 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63854.682607 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.712468 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63759.994524 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 348 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 8606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 8605 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15978 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4627 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 20605 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 299 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 12871748 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3552548 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 3949 # Transaction distribution
-system.membus.trans_dist::ReadResp 3949 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 345 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 345 # Transaction distribution
+system.membus.trans_dist::ReadReq 3944 # Transaction distribution
+system.membus.trans_dist::ReadResp 3944 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 298 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 298 # Transaction distribution
system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 350528 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 5827 # Request fanout histogram
+system.membus.snoop_fanout::samples 5775 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5775 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5827 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 5775 # Request fanout histogram
+system.membus.reqLayer0.occupancy 6990000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 29627952 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 21143500 # Number of ticks simulated
final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 36086 # Simulator instruction rate (inst/s)
-host_op_rate 65370 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 141788196 # Simulator tick rate (ticks/s)
-host_mem_usage 241940 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 30354 # Simulator instruction rate (inst/s)
+host_op_rate 54988 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 119268705 # Simulator tick rate (ticks/s)
+host_mem_usage 303472 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.numCycles 42288 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 12201 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 23748 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.168519 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.673732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 19483 82.04% 82.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 236 0.99% 83.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 173 0.73% 83.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 257 1.08% 84.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 208 0.88% 85.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 228 0.96% 86.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 337 1.42% 88.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 205 0.86% 88.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2621 11.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 23748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle
+system.cpu.decode.IdleCycles 11953 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3332 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 12221 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3474 # Number of cycles rename is running
system.cpu.iq.iqSquashedInstsExamined 11697 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 23748 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.752990 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.715169 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 18623 78.42% 78.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1142 4.81% 83.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 888 3.74% 86.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 640 2.69% 89.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 832 3.50% 93.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 584 2.46% 95.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 601 2.53% 98.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 23748 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available
system.cpu.iq.rate 0.422862 # Inst issue rate
system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 59806 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 33148 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 21784 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.447438 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.339216 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 18538 85.10% 85.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1010 4.64% 89.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 544 2.50% 92.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 738 3.39% 95.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 369 1.69% 97.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 141 0.65% 97.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 113 0.52% 98.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 72 0.33% 98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 259 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 21784 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 43058 # The number of ROB reads
+system.cpu.rob.rob_reads 42968 # The number of ROB reads
system.cpu.rob.rob_writes 44876 # The number of ROB writes
-system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 18540 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction
projects / gem5.git / commitdiff