Blackboxes

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 9653fe5b80cfd14aa591cb0f2efd548234e52354..4d907c7e25b656e9379ac0a878c6436638968e86 100644 (file)
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -3,18 +3,18 @@
 # F7BMUX slower than F7AMUX
 # Inputs: I0 I1 S0
 # Outputs: O
-F7BMUX 1 1 3 1
+F7BMUX 1 0 3 1
 217 223 296
 
 # Inputs: I0 I1 S0
 # Outputs: O
-MUXF8 2 1 3 1
+MUXF8 2 0 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
-CARRY4 3 1 10 8
+CARRY4 3 0 10 8
 271 536 379 -   -   -   340 -   -   -
 157 494 465 445 -   -   433 469 -   -
 228 592 540 520 356 -   512 548 292 -
@@ -27,13 +27,13 @@ CARRY4 3 1 10 8
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 4 1 15 2
+RAM64X1D 4 0 15 2
 -   -   -   -   -   -   - 124 124 124 124 124 124 - -
 124 124 124 124 124 124 - -   -   -   -   -   124 - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 5 1 17 2
+RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 29c79f68999dbce3b72c43844b59f4bb1ef1501a..db47b4230bb2ec848fffde868e6c5a211b3d102c 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1, lib_whitebox *)
+(* abc_box_id = 1 /*, lib_whitebox*/ *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2, lib_whitebox *)
+(* abc_box_id = 2 /*, lib_whitebox*/ *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
@@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, lib_whitebox *)
+(* abc_box_id = 3 /*, lib_whitebox*/ *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
+(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -301,7 +301,7 @@ module RAM64X1D (
 `endif
 endmodule
 
-(* abc_box_id = 5, lib_whitebox *)
+(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,