checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
arch/alpha/ev5.cc:
XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
--HG--
extra : convert_revision :
be4c0247e5834005c60a45796a222cffd327b64e
}
-template <class XC>
+template <class CPU>
void
-AlphaISA::processInterrupts(XC *xc)
+AlphaISA::processInterrupts(CPU *cpu)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
int ipl = 0;
int summary = 0;
- IntReg *ipr = xc->getIprPtr();
+ IntReg *ipr = cpu->getIprPtr();
- check_interrupts = 0;
+ cpu->checkInterrupts = false;
if (ipr[IPR_ASTRR])
panic("asynchronous traps not implemented\n");
}
}
- uint64_t interrupts = xc->intr_status();
+ uint64_t interrupts = cpu->intr_status();
if (interrupts) {
for (int i = INTLEVEL_EXTERNAL_MIN;
if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
- xc->trap(Interrupt_Fault);
+ cpu->trap(Interrupt_Fault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
}
}
-template <class XC>
+template <class CPU>
void
-AlphaISA::zeroRegisters(XC *xc)
+AlphaISA::zeroRegisters(CPU *cpu)
{
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
- xc->xc->setIntReg(ZeroReg, 0);
- xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+ cpu->xc->setIntReg(ZeroReg, 0);
+ cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
// that's it! (orders of magnitude less painful than x86)
}
-bool AlphaISA::check_interrupts = false;
-
Fault
ExecContext::hwrei()
{
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(®s, false);
- AlphaISA::check_interrupts = true;
+ cpu->checkInterrupts = true;
}
// FIXME: XXX check for interrupts? XXX
Counter max_loads_any_thread,
Counter max_loads_all_threads,
System *_system, Tick freq)
- : SimObject(_name), frequency(freq), deferRegistration(_def_reg),
- number_of_threads(_number_of_threads), system(_system)
+ : SimObject(_name), frequency(freq), checkInterrupts(true),
+ deferRegistration(_def_reg), number_of_threads(_number_of_threads),
+ system(_system)
#else
BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
Counter max_insts_any_thread,
if (index < 0 || index >= sizeof(uint64_t) * 8)
panic("int_num out of bounds\n");
- AlphaISA::check_interrupts = 1;
+ checkInterrupts = true;
interrupts[int_num] |= 1 << index;
intstatus |= (ULL(1) << int_num);
}
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
+ bool checkInterrupts;
bool check_interrupt(int int_num) const {
if (int_num > NumInterruptLevels)
Fault fault = No_Fault;
#ifdef FULL_SYSTEM
- if (AlphaISA::check_interrupts &&
- xc->cpu->check_interrupts() &&
- !PC_PAL(xc->regs.pc) &&
+ if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
status() != IcacheMissComplete) {
int ipl = 0;
int summary = 0;
- AlphaISA::check_interrupts = 0;
+ checkInterrupts = false;
IntReg *ipr = xc->regs.ipr;
if (xc->regs.ipr[TheISA::IPR_SIRR]) {