kernel: SigSpec use more const& + overloads to prevent implicit SigSpec

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4ba66f26bdce4f53624d7c8d08c4bbb74ffbb3ab..102b3024128d47cab3874b7776d3ea4ffc752824 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1599,11 +1599,17 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
                        rhs.unpack();
                        for (int i = 0; i < GetSize(lhs); i++) {
                                RTLIL::SigBit &lhs_bit = lhs.bits_[i];
-                               if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
+                               if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) {
+                                       lhs_bit.wire = module->addWire(NEW_ID);
+                                       lhs_bit.offset = 0;
                                        continue;
+                               }
                                RTLIL::SigBit &rhs_bit = rhs.bits_[i];
-                               if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
+                               if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) {
+                                       rhs_bit.wire = module->addWire(NEW_ID);
+                                       rhs_bit.offset = 0;
                                        continue;
+                               }
                        }
                }
        };
@@ -2798,9 +2804,11 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
        width_ = 0;
        hash_ = 0;
 
-       std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
-       for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
-               append(*it);
+       log_assert(parts.size() > 0);
+       auto ie = parts.begin();
+       auto it = ie + parts.size() - 1;
+       while (it >= ie)
+               append(*it--);
 }
 
 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
@@ -2844,7 +2852,7 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
 {
        cover("kernel.rtlil.sigspec.init.const");
 
-       chunks_.push_back(RTLIL::SigChunk(value));
+       chunks_.emplace_back(value);
        width_ = chunks_.back().width;
        hash_ = 0;
        check();
@@ -2854,7 +2862,7 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
 {
        cover("kernel.rtlil.sigspec.init.chunk");
 
-       chunks_.push_back(chunk);
+       chunks_.emplace_back(chunk);
        width_ = chunks_.back().width;
        hash_ = 0;
        check();
@@ -2864,7 +2872,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
 {
        cover("kernel.rtlil.sigspec.init.wire");
 
-       chunks_.push_back(RTLIL::SigChunk(wire));
+       chunks_.emplace_back(wire);
        width_ = chunks_.back().width;
        hash_ = 0;
        check();
@@ -2874,7 +2882,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
 {
        cover("kernel.rtlil.sigspec.init.wire_part");
 
-       chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
+       chunks_.emplace_back(wire, offset, width);
        width_ = chunks_.back().width;
        hash_ = 0;
        check();
@@ -2884,7 +2892,7 @@ RTLIL::SigSpec::SigSpec(const std::string &str)
 {
        cover("kernel.rtlil.sigspec.init.str");
 
-       chunks_.push_back(RTLIL::SigChunk(str));
+       chunks_.emplace_back(str);
        width_ = chunks_.back().width;
        hash_ = 0;
        check();
@@ -2894,7 +2902,7 @@ RTLIL::SigSpec::SigSpec(int val, int width)
 {
        cover("kernel.rtlil.sigspec.init.int");
 
-       chunks_.push_back(RTLIL::SigChunk(val, width));
+       chunks_.emplace_back(val, width);
        width_ = width;
        hash_ = 0;
        check();
@@ -2904,18 +2912,18 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
 {
        cover("kernel.rtlil.sigspec.init.state");
 
-       chunks_.push_back(RTLIL::SigChunk(bit, width));
+       chunks_.emplace_back(bit, width);
        width_ = width;
        hash_ = 0;
        check();
 }
 
-RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
+RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
 {
        cover("kernel.rtlil.sigspec.init.bit");
 
        if (bit.wire == NULL)
-               chunks_.push_back(RTLIL::SigChunk(bit.data, width));
+               chunks_.emplace_back(bit.data, width);
        else
                for (int i = 0; i < width; i++)
                        chunks_.push_back(bit);
@@ -2924,47 +2932,47 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
        check();
 }
 
-RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
+RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
 {
        cover("kernel.rtlil.sigspec.init.stdvec_chunks");
 
        width_ = 0;
        hash_ = 0;
-       for (auto &c : chunks)
+       for (const auto &c : chunks)
                append(c);
        check();
 }
 
-RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
+RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
 {
        cover("kernel.rtlil.sigspec.init.stdvec_bits");
 
        width_ = 0;
        hash_ = 0;
-       for (auto &bit : bits)
-               append_bit(bit);
+       for (const auto &bit : bits)
+               append(bit);
        check();
 }
 
-RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
+RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
 {
        cover("kernel.rtlil.sigspec.init.pool_bits");
 
        width_ = 0;
        hash_ = 0;
-       for (auto &bit : bits)
-               append_bit(bit);
+       for (const auto &bit : bits)
+               append(bit);
        check();
 }
 
-RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
+RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
 {
        cover("kernel.rtlil.sigspec.init.stdset_bits");
 
        width_ = 0;
        hash_ = 0;
-       for (auto &bit : bits)
-               append_bit(bit);
+       for (const auto &bit : bits)
+               append(bit);
        check();
 }
 
@@ -2974,7 +2982,7 @@ RTLIL::SigSpec::SigSpec(bool bit)
 
        width_ = 0;
        hash_ = 0;
-       append_bit(bit);
+       append(SigBit(bit));
        check();
 }
 
@@ -3292,14 +3300,14 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLI
                                        bits_match[i].wire == pattern_chunk.wire &&
                                        bits_match[i].offset >= pattern_chunk.offset &&
                                        bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
-                                       ret.append_bit(bits_other[i]);
+                                       ret.append(bits_other[i]);
                } else {
                        for (int i = 0; i < width_; i++)
                                if (bits_match[i].wire &&
                                        bits_match[i].wire == pattern_chunk.wire &&
                                        bits_match[i].offset >= pattern_chunk.offset &&
                                        bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
-                                       ret.append_bit(bits_match[i]);
+                                       ret.append(bits_match[i]);
                }
        }
 
@@ -3323,11 +3331,11 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const
                std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
                for (int i = 0; i < width_; i++)
                        if (bits_match[i].wire && pattern.count(bits_match[i]))
-                               ret.append_bit(bits_other[i]);
+                               ret.append(bits_other[i]);
        } else {
                for (int i = 0; i < width_; i++)
                        if (bits_match[i].wire && pattern.count(bits_match[i]))
-                               ret.append_bit(bits_match[i]);
+                               ret.append(bits_match[i]);
        }
 
        ret.check();
@@ -3449,7 +3457,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
        check();
 }
 
-void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
+void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
 {
        if (packed())
        {

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 451bdd7b6b0125fb5404076fbf1968250ec005f7..4c855fdfd0d9ca21eea265610effc22ad4a6bc26 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -775,11 +775,11 @@ public:
        SigSpec(const std::string &str);
        SigSpec(int val, int width = 32);
        SigSpec(RTLIL::State bit, int width = 1);
-       SigSpec(RTLIL::SigBit bit, int width = 1);
-       SigSpec(std::vector<RTLIL::SigChunk> chunks);
-       SigSpec(std::vector<RTLIL::SigBit> bits);
-       SigSpec(pool<RTLIL::SigBit> bits);
-       SigSpec(std::set<RTLIL::SigBit> bits);
+       SigSpec(const RTLIL::SigBit& bit, int width = 1);
+       SigSpec(const std::vector<RTLIL::SigChunk>& chunks);
+       SigSpec(const std::vector<RTLIL::SigBit>& bits);
+       SigSpec(const pool<RTLIL::SigBit>& bits);
+       SigSpec(const std::set<RTLIL::SigBit>& bits);
        SigSpec(bool bit);
 
        SigSpec(RTLIL::SigSpec &&other) {
@@ -849,7 +849,13 @@ public:
        RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
 
        void append(const RTLIL::SigSpec &signal);
-       void append_bit(const RTLIL::SigBit &bit);
+       inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }
+       inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }
+       inline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }
+
+       void append(const RTLIL::SigBit &bit);
+       inline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }
+       inline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }
 
        void extend_u0(int width, bool is_signed = false);
 
@@ -1469,7 +1475,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
 inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
-inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;}
+inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; }
 
 inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
        if (wire == other.wire)

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index eb912cfd44e6c8feb61a0433eacbe16485ee421e..0c8f9b172d8f220002a04c39d7cb7c25f8654635 100644 (file)
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -120,8 +120,8 @@ struct MemoryShareWorker
                for (auto &cond : conditions) {
                        RTLIL::SigSpec sig1, sig2;
                        for (auto &it : cond) {
-                               sig1.append_bit(it.first);
-                               sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
+                               sig1.append(it.first);
+                               sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
                        }
                        terms.append(module->Ne(NEW_ID, sig1, sig2));
                        created_conditions++;
@@ -284,8 +284,8 @@ struct MemoryShareWorker
                        std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
                        if (groups.count(key) == 0) {
                                groups[key].first = grouped_bits.size();
-                               grouped_bits.append_bit(v_bits[i]);
-                               grouped_mask_bits.append_bit(v_mask_bits[i]);
+                               grouped_bits.append(v_bits[i]);
+                               grouped_mask_bits.append(v_mask_bits[i]);
                        }
                        groups[key].second.push_back(i);
                }
@@ -295,7 +295,7 @@ struct MemoryShareWorker
 
                for (int i = 0; i < bits.size(); i++) {
                        std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
-                       result.append_bit(grouped_result.at(groups.at(key).first));
+                       result.append(grouped_result.at(groups.at(key).first));
                }
 
                return result;
@@ -326,7 +326,7 @@ struct MemoryShareWorker
 
                for (int i = 0; i < int(v_old_en.size()); i++) {
                        std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
-                       new_merged_en.append_bit(grouped_new_en.at(groups.at(key)));
+                       new_merged_en.append(grouped_new_en.at(groups.at(key)));
                }
 
                // Create the new merged_data signal.
@@ -635,8 +635,8 @@ struct MemoryShareWorker
                        for (int j = 0; j < int(this_en.size()); j++) {
                                std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
                                if (!groups_en.count(key)) {
-                                       grouped_last_en.append_bit(last_en[j]);
-                                       grouped_this_en.append_bit(this_en[j]);
+                                       grouped_last_en.append(last_en[j]);
+                                       grouped_this_en.append(this_en[j]);
                                        groups_en[key] = grouped_en->width;
                                        grouped_en->width++;
                                }

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index cac265a52d966f5a38c7a1d58b5dda5ccff5d55a..07f9ee2a0911ec338f5dfea4fbe797d1fc7ef6c1 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -203,8 +203,8 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
                return !(w2->port_input && w2->port_output);
 
        if (w1->name[0] == '\\' && w2->name[0] == '\\') {
-               if (regs.check_any(s1) != regs.check_any(s2))
-                       return regs.check_any(s2);
+               if (regs.check(s1) != regs.check(s2))
+                       return regs.check(s2);
                if (direct_wires.count(w1) != direct_wires.count(w2))
                        return direct_wires.count(w2) != 0;
                if (conns.check_any(s1) != conns.check_any(s2))
@@ -358,8 +358,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
                                                s2[i] = initval[i];
                                                initval[i] = State::Sx;
                                        }
-                                       new_conn.first.append_bit(s1[i]);
-                                       new_conn.second.append_bit(s2[i]);
+                                       new_conn.first.append(s1[i]);
+                                       new_conn.second.append(s2[i]);
                                }
                        if (new_conn.first.size() > 0) {
                                if (initval.is_fully_undef())

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 4a2f170b83401acaa02b2a4944cc1ae8ca556235..882d49a90e3d753eba0f1aeb07892d19578ce48b 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -193,11 +193,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 
                for (auto &it : grouped_bits[i]) {
                        for (auto &bit : it.second) {
-                               new_conn.first.append_bit(bit);
-                               new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size()));
+                               new_conn.first.append(bit);
+                               new_conn.second.append(RTLIL::SigBit(new_y, new_a.size()));
                        }
-                       new_a.append_bit(it.first.first);
-                       new_b.append_bit(it.first.second);
+                       new_a.append(it.first.first);
+                       new_b.append(it.first.second);
                }
 
                if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) {

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index f74655d1ced393734b3626769aa51abcdb0addaf..fd734c387ec6036ef7c90c325c14a32a0666135f 100644 (file)
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -192,13 +192,13 @@ struct OptReduceWorker
 
                        if (all_tuple_bits_same)
                        {
-                               old_sig_conn.first.append_bit(sig_y.at(i));
-                               old_sig_conn.second.append_bit(sig_a.at(i));
+                               old_sig_conn.first.append(sig_y.at(i));
+                               old_sig_conn.second.append(sig_a.at(i));
                        }
                        else if (consolidated_in_tuples_map.count(in_tuple))
                        {
-                               old_sig_conn.first.append_bit(sig_y.at(i));
-                               old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
+                               old_sig_conn.first.append(sig_y.at(i));
+                               old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple));
                        }
                        else
                        {

diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 92b5794acc9875bace927df2b5f781a693887bc4..a7fefc29130e1e236468c893bc4f5c62df1967e1 100644 (file)
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -331,7 +331,7 @@ struct Pmux2ShiftxPass : public Pass {
                                        pair<SigSpec, Const> entry;
 
                                        for (auto it : bits) {
-                                               entry.first.append_bit(it.first);
+                                               entry.first.append(it.first);
                                                entry.second.bits.push_back(it.second);
                                        }
 
@@ -352,7 +352,7 @@ struct Pmux2ShiftxPass : public Pass {
                                        pair<SigSpec, Const> entry;
 
                                        for (auto it : bits) {
-                                               entry.first.append_bit(it.first);
+                                               entry.first.append(it.first);
                                                entry.second.bits.push_back(it.second);
                                        }
 

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 92ce3fd11d825009c3db4b5f39948ff2dae22207..611a7862b4fdba4135836790f7c97395d54e5e90 100644 (file)
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -516,7 +516,7 @@ struct ShareWorker
                                if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
                                        unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
                                        RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
-                                       new_a.append_bit(RTLIL::State::S0);
+                                       new_a.append(RTLIL::State::S0);
                                        unsigned_cell->setPort(ID::A, new_a);
                                }
                                unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
@@ -588,7 +588,7 @@ struct ShareWorker
                                if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
                                        unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
                                        RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
-                                       new_a.append_bit(RTLIL::State::S0);
+                                       new_a.append(RTLIL::State::S0);
                                        unsigned_cell->setPort(ID::A, new_a);
                                }
                                unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
@@ -601,7 +601,7 @@ struct ShareWorker
                                if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
                                        unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
                                        RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
-                                       new_b.append_bit(RTLIL::State::S0);
+                                       new_b.append(RTLIL::State::S0);
                                        unsigned_cell->setPort(ID::B, new_b);
                                }
                                unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
@@ -790,7 +790,7 @@ struct ShareWorker
                p.second.bits.clear();
 
                for (auto &it : p_bits) {
-                       p.first.append_bit(it.first);
+                       p.first.append(it.first);
                        p.second.bits.push_back(it.second);
                }
 
@@ -906,14 +906,14 @@ struct ShareWorker
                        if (used_in_a)
                                for (auto p : c_patterns) {
                                        for (int i = 0; i < GetSize(sig_s); i++)
-                                               p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
+                                               p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
                                        if (sort_check_activation_pattern(p))
                                                activation_patterns_cache[cell].insert(p);
                                }
 
                        for (int idx : used_in_b_parts)
                                for (auto p : c_patterns) {
-                                       p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
+                                       p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
                                        if (sort_check_activation_pattern(p))
                                                activation_patterns_cache[cell].insert(p);
                                }
@@ -948,7 +948,7 @@ struct ShareWorker
 
                RTLIL::SigSpec signal;
                for (auto &bit : all_bits)
-                       signal.append_bit(bit);
+                       signal.append(bit);
 
                return signal;
        }
@@ -963,7 +963,7 @@ struct ShareWorker
 
                        for (int i = 0; i < GetSize(p_first); i++)
                                if (filter_bits.count(p_first[i]) == 0) {
-                                       new_p.first.append_bit(p_first[i]);
+                                       new_p.first.append(p_first[i]);
                                        new_p.second.bits.push_back(p.second.bits.at(i));
                                }
 

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 04b882db9210380fde46cc96cbca81653a3af37d..b5451849de0af8bd9a0957fda6ba6ae051673339 100644 (file)
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -98,7 +98,7 @@ struct WreduceWorker
 
                SigSpec sig_removed;
                for (int i = GetSize(bits_removed)-1; i >= 0; i--)
-                       sig_removed.append_bit(bits_removed[i]);
+                       sig_removed.append(bits_removed[i]);
 
                if (GetSize(bits_removed) == GetSize(sig_y)) {
                        log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));

diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index d4aee9df02d12c5a5f38fc798e2c7ab2c4689567..caf938a74b3627d953a419a75bc37fb199ea2a53 100644 (file)
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -93,7 +93,7 @@ struct PruneWorker
                                                for (int i = 0; i < GetSize(lhs); i++) {
                                                        RTLIL::SigBit lhs_bit = lhs[i];
                                                        if (lhs_bit.wire && !assigned[lhs_bit]) {
-                                                               conn.first.append_bit(lhs_bit);
+                                                               conn.first.append(lhs_bit);
                                                                conn.second.append(rhs.extract(i));
                                                        }
                                                }

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index f9e7783a906e64ddf424eb0abe3c11f1142eb3f6..24aba22f3efa965e0d010dced19aa9e893226cef 100644 (file)
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass {
                                                SigSpec clock_edge_pattern;
 
                                                if (clkpol) {
-                                                       clock_edge_pattern.append_bit(State::S0);
-                                                       clock_edge_pattern.append_bit(State::S1);
+                                                       clock_edge_pattern.append(State::S0);
+                                                       clock_edge_pattern.append(State::S1);
                                                } else {
-                                                       clock_edge_pattern.append_bit(State::S1);
-                                                       clock_edge_pattern.append_bit(State::S0);
+                                                       clock_edge_pattern.append(State::S1);
+                                                       clock_edge_pattern.append(State::S0);
                                                }
 
                                                SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
@@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass {
                                        SigSpec clock_edge_pattern;
 
                                        if (clkpol) {
-                                               clock_edge_pattern.append_bit(State::S0);
-                                               clock_edge_pattern.append_bit(State::S1);
+                                               clock_edge_pattern.append(State::S0);
+                                               clock_edge_pattern.append(State::S1);
                                        } else {
-                                               clock_edge_pattern.append_bit(State::S1);
-                                               clock_edge_pattern.append_bit(State::S0);
+                                               clock_edge_pattern.append(State::S1);
+                                               clock_edge_pattern.append(State::S0);
                                        }
 
                                        SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);

diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 11cfddcd9c39889f85947b3f069372c2f3fa587e..92c52398c6ac8f1e646a1dab54496d47b4d55cf5 100644 (file)
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass
                                                SigSpec input;
                                                for (auto b : input_pool)
                                                        if (input_pool_intermed.count(b) == 0)
-                                                               input.append_bit(b);
+                                                               input.append(b);
 
                                                SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
 

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index a2ad87f7d279ac5868e8d81c8463ff63f2612bff..427b72a6a47b71d48aaa8b95190c9c9b52088d65 100644 (file)
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -1405,7 +1405,7 @@ struct FlowmapWorker
 
                        RTLIL::SigSpec lut_a, lut_y = node;
                        for (auto input_node : input_nodes)
-                               lut_a.append_bit(input_node);
+                               lut_a.append(input_node);
                        lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
 
                        RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0c57733d41f1996a49f0df06d9bc3f28ee4abf71..5ddc18a121efaf220b8783025ab2ad1a0cb4272e 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -906,8 +906,8 @@ struct TechmapWorker
 
                                                                RTLIL::SigSig port_conn;
                                                                for (auto &it : port_connmap) {
-                                                                       port_conn.first.append_bit(it.first);
-                                                                       port_conn.second.append_bit(it.second);
+                                                                       port_conn.first.append(it.first);
+                                                                       port_conn.second.append(it.second);
                                                                }
                                                                tpl->connect(port_conn);