[AArch64] Add more SVE FMLA and FMAD /z alternatives

This patch makes the floating-point conditional FMA patterns provide the
same /z alternatives as the integer patterns added by a previous patch.
We can handle cases in which individual inputs are allocated to the same
register as the output, so we don't need to force all registers to be
different.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
	alternatives in which one of the inputs is in the same register
	as the output.

gcc/testsuite/
	* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
	and FMSB as well as FMLS.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274516

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb39212683cbd407b53954e9ab46cbc84e789863..0fd607e46bb4ca383238e76d62b309a8167b10da 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
+           Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
+
+       * config/aarch64/aarch64-sve.md
+       (*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
+       alternatives in which one of the inputs is in the same register
+       as the output.
+
 2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/aarch64-sve.md (*vec_extract<mode><Vel>_ext)

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 9007a79d0e974a260227768555158b1d121c783a..c5d7801a3cec1549a0f524a8f6b77009a3435607 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3844,17 +3844,17 @@
 ;; Predicated floating-point ternary operations, merging with an
 ;; independent value.
 (define_insn_and_rewrite "*cond_<optab><mode>_any"
-  [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w")
+  [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w")
        (unspec:SVE_F
-         [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+         [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
           (unspec:SVE_F
             [(match_operand 6)
              (match_operand:SI 7 "aarch64_sve_gp_strictness")
-             (match_operand:SVE_F 2 "register_operand" "w, w, w")
-             (match_operand:SVE_F 3 "register_operand" "w, w, w")
-             (match_operand:SVE_F 4 "register_operand" "w, w, w")]
+             (match_operand:SVE_F 2 "register_operand" "w, w, 0, w, w, w")
+             (match_operand:SVE_F 3 "register_operand" "w, w, w, 0, w, w")
+             (match_operand:SVE_F 4 "register_operand" "w, 0, w, w, w, w")]
             SVE_COND_FP_TERNARY)
-          (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, 0, w")]
+          (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && !rtx_equal_p (operands[2], operands[5])
@@ -3863,6 +3863,9 @@
    && aarch64_sve_pred_dominates_p (&operands[6], operands[1])"
   "@
    movprfx\t%0.<Vetype>, %1/z, %4.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmad_op>\t%0.<Vetype>, %1/m, %3.<Vetype>, %4.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmad_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %4.<Vetype>
    movprfx\t%0.<Vetype>, %1/m, %4.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
    #"
   "&& 1"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 731249adbdf5963752e42d4d268fd55977affdc1..308386c703c16a972e412920b3b9fbfa6b5560dd 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
+           Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
+
+       * gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
+       and FMSB as well as FMLS.
+
 2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
 
        * gcc.target/aarch64/sve/ext_2.c: Expect a MOVPRFX.

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c
index e71f2b0336ff84ced19026d8e4901e3db1cbd5f0..97e2335799602757ae99690909deee4746802d43 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c
@@ -39,13 +39,13 @@ TEST_ALL (DEF_LOOP)
 /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
 /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
+/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
 
 /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z,} 2 } } */
 /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z,} 4 } } */