add extra test_pysvp64dis.py test for ff=~RC1/vli mode

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index cea9113ca153d794cdac360c6a347be7bd985964..9f5dd88a99a3fc940da9fe90fa7adf844b859d84 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -284,6 +284,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_17_vli(self):
         expected = [
                     "sv.add/ff=RC1/vli 3,7,11",
+                    "sv.add/ff=~RC1/vli 3,7,11",
                         ]
         self._do_tst(expected)