Cleanup

diff --git a/migen/bank/__init__.py b/migen/bank/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 8e924b4b2be54deca218bfb553efeb06506c8e09..5f70b3338f6b7b66b73013e3581a86b568a46e29 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -85,36 +85,16 @@ class Operator(Value):
        def __init__(self, op, operands):
                self.op = op
                self.operands = list(map(_cst, operands))
-       
-       def __str__(self):
-               arity = len(self.operands)
-               if arity == 1:
-                       r = self.op + str(self.operands[0])
-               elif arity == 2:
-                       r = str(self.operands[0]) + " " + self.op + " " + str(self.operands[1])
-               else:
-                       r = self.op + "(" + ", ".join(map(str, self.operands)) + ")"
-               return "(" + r + ")"
 
 class Slice(Value):
        def __init__(self, value, start, stop):
                self.value = value
                self.start = start
                self.stop = stop
-       
-       def __str__(self):
-               if self.start + 1 == self.stop:
-                       sr = "[" + str(self.start) + "]"
-               else:
-                       sr = "[" + str(self.start) + ":" + str(self.stop) + "]"
-               return str(self.value) + sr
 
 class Cat(Value):
        def __init__(self, *args):
                self.l = list(map(_cst, args))
-       
-       def __str__(self):
-               return "{" + ", ".join(map(str, self.l)) + "}"
 
 class Constant(Value):
        def __init__(self, n, bv=None):
@@ -123,12 +103,6 @@ class Constant(Value):
                else:
                        Value.__init__(self, bv)
                self.n = n
-       
-       def __str__(self):
-               if self.n >= 0:
-                       return str(self.bv) + str(self.n)
-               else:
-                       return "-" + str(self.bv) + str(-self.n)
 
 def _cst(x):
        if isinstance(x, int):
@@ -144,9 +118,6 @@ class Signal(Value):
                self.name = name
                self.reset = Constant(reset, bv)
 
-       def __str__(self):
-               return self.name
-       
        def __hash__(self):
                return id(self)
 
@@ -159,16 +130,10 @@ class Assign:
        def __init__(self, l, r):
                self.l = l
                self.r = _cst(r)
-       
-       def __str__(self):
-               return str(self.l) + " = " + str(self.r)
 
 class StatementList:
        def __init__(self, l=[]):
                self.l = l
-       
-       def __str__(self):
-               return "\n".join(map(str, self.l))
 
 def _sl(x):
        if isinstance(x, list):
@@ -176,23 +141,11 @@ def _sl(x):
        else:
                return x
 
-def _indent(s):
-       if s:
-               return "\t" + s.replace("\n", "\n\t")
-       else:
-               return ""
-               
 class If:
        def __init__(self, cond, t, f=StatementList()):
                self.cond = cond
                self.t = _sl(t)
                self.f = _sl(f)
-       
-       def __str__(self):
-               r = "if " + str(self.cond) + ":\n" + _indent(str(self.t))
-               if self.f.l:
-                       r += "\nelse:\n" + _indent(str(self.f))
-               return r
 
 class Case:
        def __init__(self, test, cases=[], default=StatementList()):
@@ -207,8 +160,5 @@ class Fragment:
                self.comb = _sl(comb)
                self.sync = _sl(sync)
        
-       def __str__(self):
-               return "Comb:\n" + _indent(str(self.comb)) + "\nSync:\n" + _indent(str(self.sync))
-       
        def __add__(self, other):
                return Fragment(self.comb.l + other.comb.l, self.sync.l + other.sync.l)
\ No newline at end of file

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d3e291a4b9486c0570e4236bd43d236bfab34e70..a79dfcc5bc6c5eb55b6b6a09baad844ceb4b6096 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -20,17 +20,20 @@ def Convert(f, outs=set(), ins=set(), name="top", clkname="sys_clk", rstname="sy
                n += ns.GetName(s)
                return n
        
-       def printnode(level, node):
+       def printexpr(node):
                if isinstance(node, Constant):
-                       return str(node)
+                       if node.n >= 0:
+                               return str(node.bv) + str(node.n)
+                       else:
+                               return "-" + str(node.bv) + str(-self.n)
                elif isinstance(node, Signal):
                        return ns.GetName(node)
                elif isinstance(node, Operator):
                        arity = len(node.operands)
                        if arity == 1:
-                               r = self.op + str(node.operands[0])
+                               r = self.op + printexpr(node.operands[0])
                        elif arity == 2:
-                               r = printnode(level, node.operands[0]) + " " + node.op + " " + printnode(level, node.operands[1])
+                               r = printexpr(node.operands[0]) + " " + node.op + " " + printexpr(node.operands[1])
                        else:
                                raise TypeError
                        return "(" + r + ")"
@@ -39,18 +42,22 @@ def Convert(f, outs=set(), ins=set(), name="top", clkname="sys_clk", rstname="sy
                                sr = "[" + str(node.start) + "]"
                        else:
                                sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
-                       return str(node.value) + sr
+                       return printexpr(node.value) + sr
                elif isinstance(node, Cat):
-                       l = list(map(partial(printnode, level), node.l))
+                       l = list(map(printexpr, node.l))
                        l.reverse()
                        return "{" + ", ".join(l) + "}"
-               elif isinstance(node, Assign):
+               else:
+                       raise TypeError
+       
+       def printnode(level, node):
+               if isinstance(node, Assign):
                        # TODO: variables
-                       return "\t"*level + printnode(level, node.l) + " <= " + printnode(level, node.r) + ";\n"
+                       return "\t"*level + printexpr(node.l) + " <= " + printexpr(node.r) + ";\n"
                elif isinstance(node, StatementList):
                        return "".join(list(map(partial(printnode, level), node.l)))
                elif isinstance(node, If):
-                       r = "\t"*level + "if (" + printnode(level, node.cond) + ") begin\n"
+                       r = "\t"*level + "if (" + printexpr(node.cond) + ") begin\n"
                        r += printnode(level + 1, node.t)
                        if node.f.l:
                                r += "\t"*level + "end else begin\n"
@@ -58,9 +65,9 @@ def Convert(f, outs=set(), ins=set(), name="top", clkname="sys_clk", rstname="sy
                        r += "\t"*level + "end\n"
                        return r
                elif isinstance(node, Case):
-                       r = "\t"*level + "case (" + printnode(level, node.test) + ")\n"
+                       r = "\t"*level + "case (" + printexpr(node.test) + ")\n"
                        for case in node.cases:
-                               r += "\t"*(level + 1) + printnode(level, case[0]) + ": begin\n"
+                               r += "\t"*(level + 1) + printexpr(case[0]) + ": begin\n"
                                r += printnode(level + 2, case[1])
                                r += "\t"*(level + 1) + "end\n"
                        r += "\t"*level + "endcase\n"